Integrated assemblies having liners or rings surrounding regions of conductive posts

An integrated assembly, comprising:

• a memory region and another region adjacent the memory region;
• channel-material-pillars arranged within the memory region, and conductive posts arranged within said other region;
• a source structure coupled to lower regions of the channel-material-pillars, the source structure comprising at least six separate and discrete layers of material, at least two of six layers comprising different compositions;
• a panel extending across the memory region and said other region, and separating a first memory-block-region from a second memory-block-region;
• doped-semiconductor-material against the channel-material-pillars within the memory region;
• and
• a first ring surrounding each conductive post, a second ring surrounding the first ring and comprising at least-four vertically-stacked materials comprising four different materials stacked against each other, a third ring comprising a single layer of insulative material extending perpendicularly to, and through, the at least four vertically-stacked materials and surrounding the second ring.

An integrated assembly, comprising:

• a memory region and another region adjacent the memory region;
• channel-material-pillars arranged within the memory region, and conductive posts arranged within said other region;
• a source structure coupled to lower regions of the channel-material-pillars, the source structure comprising at least three separate and discrete layers of material, at least two of the three layers comprising different compositions and at least one of the three layers comprising conductive material wherein the conductive material does not comprise semiconductor material;
• a panel extending across the memory region and said other region, and separating a first memory-block-region from a second memory-block-region;
• doped-semiconductor-material directly adjacent to the panel within the memory region and the other region;
• the doped-semiconductor-material being at least part of the source structure within the memory region;
• liners comprising a first liner spaced from a second liner both extending vertically and parallel to each other and parallel with the conductive posts, the second liner laterally surrounding only lower regions of the conductive posts, the first liner comprising a first ring surrounding each conductive post:
• a second ring surrounding the first ring and comprising at least four vertically-stacked materials comprising four different materials stacked against each other, the second liner is a third ring comprising a single layer of insulative material extending perpendicularly to, and through, the at least four vertically-stacked materials and surrounding the second ring.