Integrated circuit package and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Pin Hu, Shang-Yun Hou, Shih-Wen Huang
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Abstract
A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.
Claims20
A device package comprising:
- an interposer comprising:
- a semiconductor substrate;
- first through vias extending through the semiconductor substrate, wherein the first through vias protrude from a front side of the semiconductor substrate;
- an interconnect structure over the front side of the semiconductor substrate, the interconnect structure comprising:
- a first metallization pattern in an inorganic insulating material;
- and
- a passivation film over the first metallization pattern;
- and
- a first redistribution structure over the passivation film, the first redistribution structure comprising a second metallization pattern in an organic insulating material, the organic insulating material of the first redistribution structure having the substantially same lateral extents as the inorganic insulating material of the interconnect structure and having the substantially same lateral extents as a semiconductor material of the semiconductor substrate;
- an integrated circuit die over and attached to the interposer;
- and
- a first encapsulant around the integrated circuit die.
A device package comprising:
- an interposer free of any active devices, the interposer comprising:
- a semiconductor substrate;
- an interconnect structure comprising a first metallization pattern in a first insulating material;
- and
- a first redistribution structure comprising a second metallization pattern in a second insulating material, wherein the second insulating material has a lower loss tangent than the first insulating material;
- an integrated circuit die electrically connected to the interposer, wherein the interconnect structure and the first redistribution structure are each between the integrated circuit die and the semiconductor substrate;
- a first encapsulant around the integrated circuit die, the first encapsulant completely surrounding the integrated circuit die in a plan view, outer sidewalls of the first encapsulant being coterminous with outer sidewalls of the interposer;
- and
- a second redistribution structure on an opposing side of the interposer as the integrated circuit die.
A package comprising:
- an interposer comprising:
- a semiconductor substrate;
- first through vias extending through the semiconductor substrate, wherein the first through vias protrude from a lateral surface of the semiconductor substrate;
- an interconnect structure over a first side of the semiconductor substrate, the interconnect structure comprising:
- a first metallization pattern in an inorganic insulating material;
- and
- a passivation layer over the first metallization pattern;
- and
- a first redistribution structure over the passivation layer, the first redistribution structure comprising a second metallization pattern in an organic insulating material, wherein a thickness of the first metallization pattern is less than a thickness of the second metallization pattern, and wherein the organic insulating material of the first redistribution structure has the substantially same lateral extents as a semiconductor material of the semiconductor substrate;
- an integrated circuit die bonded to the interposer;
- an underfill between the integrated circuit die and the interposer, wherein the underfill extends along a sidewall of the integrated circuit die;
- and
- a first encapsulant surrounding the integrated circuit die and the underfill, wherein the first encapsulant is coterminous with the interposer.
Dependencies are inferred from the claim text.