RRAM with a barrier layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Abstract
Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.
Claims20
An integrated chip comprising:
- a substrate;
- and
- a resistive random-access memory (RRAM) cell overlying the substrate,
- wherein the RRAM cell comprises a bottom electrode and a top electrode, and further comprises a switching layer, a barrier layer, and an active metal layer stacked between the bottom electrode and the top electrode,
- the active metal layer comprises a first metal element,
- the barrier layer comprises a second metal element and nitrogen, and
- a concentration of nitrogen in the barrier layer is different at a top of the barrier layer than at a bottom of the barrier layer.
An integrated chip comprising:
- a bottom electrode;
- a dielectric layer overlying the bottom electrode;
- a conductive filament in the dielectric layer, wherein the conductive filament extends upward from the bottom electrode;
- a barrier layer overlying the dielectric layer;
- an active metal layer overlying the barrier layer;
- and
- a top electrode overlying the active metal layer;
- wherein the bottom electrode, the top electrode, the dielectric layer, the barrier layer, and the active metal layer define a memory cell, and wherein the conductive filament is spaced from the barrier layer.
An integrated chip comprising:
- a wire;
- and
- a via dielectric layer over the wire;
- a bottom electrode overlying the via dielectric layer and extending through the via dielectric layer to the wire;
- a switching layer overlying the bottom electrode;
- a barrier layer overlying the switching layer;
- an active metal layer overlying the barrier layer;
- and
- a top electrode overlying the active metal layer;
- wherein the bottom electrode, the top electrode, the switching layer, the barrier layer, and the active metal layer define a memory cell, wherein the switching layer extends from the bottom electrode to the barrier layer, and wherein the bottom electrode is a metal or a metal nitride.
Dependencies are inferred from the claim text.