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US 12,593,619 B1Granted
System and method for electronic devices
AssigneeNational Technology & Engineering Solutions of Sandia, LLC
InventorWei Pan
Life of this patent
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Abstract
The invention includes systems and methods pertaining to Josephson effect devices. This includes electronic devices such as transistors known as Josephson Junction Field Effect Transistors (JJFETs). An electronic device is provided that has a source region including a superconductor material, a drain region including a superconductor material, a gate region between the source and drain regions, and a semiconductor region including an excitonic insulator material.
Claims19
An electronic device, comprising:
- a source region comprising a first superconductor material;
- a drain region comprising a second superconductor material;
- a gate region between the source and drain regions and comprising an oxide material and a metallic gate contact;
- and
- a semiconductor region in contact with the source region, the drain region, and the gate region, wherein the semiconductor region comprises a heterostructure comprising:
- a first barrier layer;
- a second barrier layer;
- and
- an excitonic insulator between the first barrier layer and the second barrier layer, wherein the excitonic insulator comprises:
- an InAs layer;
- and
- a GaSb layer.
9 more elements
An electronic device, comprising:
- a Boolean circuit having:
- a source region formed of a superconductor material;
- a drain region formed of the superconductor material;
- a gate region between the source region and drain region, the gate region formed of an oxide material and a metallic gate contact;
- and
- a semiconductor region in contact with the source region, the drain region, and the gate region, wherein the semiconductor region comprises a heterostructure comprising:
- a first barrier layer;
- a second barrier layer;
- and
- an excitonic insulator between the first barrier layer and the second barrier layer, wherein the excitonic insulator comprises:
- an InAs layer;
- and
- a GaSb layer.
10 more elements
A method comprising:
- forming a superconductor source region;
- forming a superconductor drain region;
- forming an oxide gate region between the source and drain regions;
- and
- forming semiconductor region in contact with the superconductor source region, the superconductor drain region, and the oxide gate region, wherein the semiconductor region comprises a heterostructure comprising:
- a first barrier layer;
- a second barrier layer;
- and
- an excitonic insulator between the first barrier layer and the second barrier layer, wherein the excitonic insulator comprises:
- an InAs layer;
- and
- a GaSb layer.
9 more elements
Dependencies are inferred from the claim text.