Pillar-shaped semiconductor device and method for producing the same
AssigneeUnisantis Electronics Singapore Pte. Ltd.
InventorNozomu Harada
Life of this patent
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Abstract
An N+ layer and a P+ layer that are impurity regions at a bottom portion are formed using as etching masks top first mask material layers and SiN layers surrounding Si pillars and formed in a self-aligned manner with respect to the Si pillars and a SiO2 layer. Then, a SiO2 layer is formed that has an upper surface located at the level of the bottom portions of the N+ layer and the P+ layer. Then, a W layer is selectively formed on exposed side faces of the N+ layer and the P+ layer. Then, a contact hole for connection to a wire metal layer is formed above the W layer as seen in plan view.
Claims6
A pillar-shaped semiconductor device comprising:
- a first semiconductor pillar formed to stand vertically on a horizontal substrate;
- a first gate insulating layer formed around the first semiconductor pillar;
- a first gate conductor layer formed around the first gate insulating layer;
- a first impurity region formed at a top of the first semiconductor pillar, wherein the first impurity region is doped to serve as one of a source or a drain of a first surrounding gate transistor (SGT);
- a second impurity region formed at a bottom of the first semiconductor pillar, wherein the second impurity region is doped to serve as the other of the source or the drain of the first SGT;
- a first material layer formed around the first semiconductor pillar and having a lower end that terminates in contact with the second impurity region;
- and
- a first conductor layer formed all around an outer periphery of the second impurity region and all around an outer periphery of the lower end of the first material layer, wherein
- a first contact hole for connecting the first conductor layer to a first external wire conductor layer is provided in contact with the first conductor layer.
Dependencies are inferred from the claim text.