Interconnected array transistors including source and drain bus bars and fingers

A semiconductor device comprising:

• a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate as viewed from a thickness direction of the substrate;
• a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction and are provided on the first surface, the first source finger being electrically connected to the source bus bar;
• a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction and are provided on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar;
• and
• a first metal layer filled in the first via hole and having a thermal conductivity lower than a thermal conductivity of the substrate.

A semiconductor device comprising:

• a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate as viewed from a thickness direction of the substrate;
• a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction and are provided on the first surface, the first source finger being electrically connected to the source bus bar;
• a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction and are provided on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar;
• a first gate bus bar provided on the first surface between the plurality of first transistors and the source bus bar and electrically connected to the first gate finger;
• and
• a second gate bus bar provided on the first surface between the plurality of second transistors and the source bus bar and electrically connected to the second gate finger;
• and
• a first source wiring electrically connecting the first source finger and the source bus bar and intersecting the first gate bus bar in a non-contact manner;
• and
• a second source wiring electrically connecting the second source finger and the source bus bar and intersecting the second gate bus bar in the non-contact manner.