Stacked fork sheet devices

A semiconductor structure comprising:

• a first pair of stacked devices that are located in a first active device region, wherein the first pair of stacked devices are separated by a first inter-device dielectric pillar and each stacked device of the first pair of stacked devices comprises a second field effect transistor (FET) stacked over a first FET;
• a second pair of stacked devices that are located in a second active device region, wherein the second pair of stacked devices are separated by a second inter-device dielectric pillar and each stacked device of the second pair of stacked devices comprises a second FET stacked over a first FET;
• and
• a local interconnect structure located in a non-active device region that is positioned between the first active device region and the second active device region, wherein the local interconnect structure is connected to a back side power distribution network and to a source/drain region of the second FET of the second pair of stacked devices that is located on a first side of the second inter-device dielectric pillar that is closest to the non-active device region.