Integrated circuit in hybrid row height structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
Life of this patent
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Abstract
An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.
Claims20
An integrated circuit, comprising:
- a first cell having a first height along a first direction;
- and
- a second cell having a second height shorter than the first height along the first direction,
- wherein a transistor of the first cell and a transistor of the second cell share a first active area,
- a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction,
- the first cell is at least formed by the first active area and a second active area,
- the second cell is at least formed by the first active area and a third active area,
- the first active area, the second active area and the third active area are separated from each other along the first direction,
- the second active area is wider than the first active area along the first direction, and
- the third active area is wider than the first active area along the first direction.
An integrated circuit, comprising:
- a first cell having a height along a first direction;
- and
- a second cell having the height along the first direction,
- wherein at least one transistor of the first cell and at least one transistor of the second cell share each of a first active area and a second active area,
- a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction,
- the first cell is formed by the first active area, the second active area and a third active area,
- the second cell is formed by the first active area, the second active area and a fourth active area, and
- the third active area, the second active area, the first active area and the fourth active area are separated from each other and arranged in order along the first direction.
An integrated circuit, comprising:
- a first cell comprising:
- a first circuit arranged in a first cell row having a first row height, the first circuit comprising at least one first transistor having a two-fins active area structure;
- a second circuit arranged in a portion of a second cell row, the second circuit comprising at least one second transistor having a first one-fin active area structure;
- and
- a third circuit arranged in a portion of a third cell row, the third circuit comprising at least one third transistor having a second one-fin active area structure;
- and
- a second cell separated from the first cell, and sharing the first one-fin active area structure with the first cell,
- wherein the portion of the second cell row has a second row height that is smaller than the first row height, and the portion of the third cell row has a third row height that is smaller than the first row height,
- wherein the first cell has a cell height that equals to the first row height plus the second row height and the third row height.
Dependencies are inferred from the claim text.