Multiple threshold voltage implementation through lanthanum incorporation

A device comprising:

• a bulk semiconductor substrate;
• a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin over the bulk semiconductor substrate;
• a first gate stack on a first sidewall and a first top surface of the first semiconductor fin, the first gate stack comprising:
• a first interfacial layer;
• a first high-k dielectric on the first interfacial layer, wherein the first high-k dielectric has a first lanthanum atomic percentage;
• and
• a conductive layer over and contacting the first high-k dielectric, wherein a peak lanthanum atomic percentage is at an interface between the first high-k dielectric and the conductive layer;
• a second gate stack on a second sidewall and a second top surface of the second semiconductor fin, the second gate stack comprising:
• a second interfacial layer;
• and
• a second high-k dielectric on the second interfacial layer, wherein the second high-k dielectric has a second lanthanum atomic percentage lower than the first lanthanum atomic percentage;
• and
• a third gate stack on a third sidewall and a third top surface of the third semiconductor fin, the third gate stack comprising:
• a third interfacial layer;
• and
• a third high-k dielectric on the third interfacial layer, wherein the third high-k dielectric has a third lanthanum atomic percentage lower than the second lanthanum atomic percentage.

A device comprising:

• a first semiconductor region and a second semiconductor region;
• a first gate stack comprising:
• a first gate dielectric on the first semiconductor region, wherein the first gate dielectric comprises first elements and a doping metal, and wherein the first gate dielectric has a first atomic percentage of the doping metal;
• and
• a first work function layer over the first gate dielectric;
• a first source/drain region aside of the first gate stack;
• a second gate stack comprising:
• a second gate dielectric on the second semiconductor region, wherein the second gate dielectric comprises second elements and the doping metal, wherein the first elements are same as the second elements, wherein the second gate dielectric has a second atomic percentage of the doping metal, and wherein the second atomic percentage is lower than the first atomic percentage;
• and
• a second work function layer over the second gate dielectric, wherein the first work function layer and the second work function layer comprise same elements;
• and
• a second source/drain region aside of the second gate stack, wherein both of the first source/drain region and the second source/drain region are n-type semiconductor regions.