Semiconductor structure including gate spacer layer and dielectric layer having portion lower than top surface of gate spacer layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHong-Chih Chen, Ta-Chun Lin, Jhon-Jhy Liaw
Life of this patent
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Abstract
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure penetrates through the first dielectric layer, and a top surface of the gate structure is higher than a top surface of the S/D contact structure.
Claims20
A semiconductor structure, comprising:
- a gate structure formed over a substrate;
- a source/drain (S/D) structure formed adjacent to the gate structure;
- a first dielectric layer formed over the S/D structure;
- an S/D contact structure formed over the S/D structure, wherein:
- the S/D contact structure penetrates through the first dielectric layer, and
- a top surface of the gate structure is higher than a top surface of the S/D contact structure;
- a gate spacer layer adjacent to the gate structure;
- and
- a second dielectric layer formed on the gate structure, wherein a portion of the second dielectric layer is lower than a top surface of the gate spacer layer.
A semiconductor structure, comprising:
- a plurality of nanostructures formed over a substrate;
- a gate electrode layer formed over the nanostructures;
- a gate spacer layer formed adjacent to the gate electrode layer;
- a source/drain (S/D) structure formed adjacent to the gate electrode layer;
- a first dielectric layer formed over the S/D structure;
- an S/D contact structure formed over the S/D structure, wherein:
- the S/D contact structure penetrates through the first dielectric layer,
- the S/D contact structure has a recessed top surface, and
- the recessed top surface of the S/D contact structure is lower than a top surface of the gate spacer layer;
- and
- a second dielectric layer formed over the first dielectric layer, wherein a portion of the second dielectric layer is lower than the top surface of the gate spacer layer.
A semiconductor structure, comprising:
- a plurality of nanostructures formed over a substrate;
- a gate electrode layer formed over the nanostructures;
- a gate spacer layer formed adjacent to the gate electrode layer;
- a source/drain (S/D) structure formed adjacent to the gate electrode layer;
- a first dielectric layer formed over the S/D structure;
- an S/D contact structure formed over the S/D structure, wherein the S/D contact structure penetrates through the first dielectric layer;
- a second dielectric layer formed over the first dielectric layer, wherein a portion of the second dielectric layer is lower than a top surface of the gate spacer layer;
- an additional conductive layer formed on the gate electrode layer;
- and
- a gate dielectric layer formed over the substrate to surround the gate electrode layer, wherein an inner sidewall of the gate dielectric layer is in direct contact with an outer sidewall of the additional conductive layer.
Dependencies are inferred from the claim text.