Trench gate type IGBT

A trench gate type IGBT, having:

• a semiconductor substrate;
• an emitter electrode, which is formed on a surface of the semiconductor substrate and an insulation film, the insulation film arranged between the emitter electrode and the semiconductor substrate;
• a collector electrode, which is formed on a back surface of the semiconductor substrate;
• a P-type P-collector layer, which is formed on a back surface side of the semiconductor substrate on the collector electrode;
• an N-type N-drift layer, which is located on the P-type P-collector layer in the semiconductor substrate;
• an N-type carrier store layer, which is formed on the N-type N-drift layer and has a higher impurity concentration than the N-type N-drift layer;
• a P-type P-body layer, which is formed on a surface side of the N-type carrier store layer of the semiconductor substrate so that a PN junction is formed between the P-type P-body layer and the N-type carrier store layer;
• a plurality of gate trenches, which are a plurality of trenches discretely formed with mesa sections interposed therebetween from a surface side of the semiconductor substrate and extending toward a back surface side to the N-type N-drift layer, and have a gate portion formed inside with an insulation film therebetween, wherein the plurality of gate trenches includes first gate trenches arranged in a gate area of the trench gate type IGBT and second gate trenches arranged in a non-gate area of the trench gate type IGBT;
• a plurality of emitter trenches, which are a plurality of trenches discretely formed with mesa sections interposed therebetween from the surface side of the semiconductor substrate and extending toward the back surface side to the N-type N-drift layer, and each has a first contact formed inside, the first contact directly connecting to the emitter electrode and extending through the insulation film;
• an emitter region, which is adjacent to one of the first gate trenches of the plurality of gate trenches, is formed on a surface side of the P-type P-body layer, and is electrically connected to the emitter electrode;
• a first mesa region, which is the P-type P-body layer of the mesa section in the gate area of the trench gate type IGBT, is connected to the emitter electrode by a second contact, and functions as a channel by forming the emitter region on the surface side of the semiconductor substrate, wherein the emitter region is arranged between the first mesa region and the emitter electrode;
• and
• a second mesa region, which is the P-type P-body layer of the mesa section in the non-gate area of the trench gate type IGBT, is connected to the emitter electrode by the first contact, and does not function as a channel due to not forming the emitter region on the surface side of the semiconductor substrate;
• wherein, in the non-gate area of the trench gate type IGBT, one of the second gate trenches is arranged between successive emitter trenches and the one of the second gate trenches and the emitter trenches are capacitively coupled.