Cell design for MOS-controlled power semiconductor device

A power semiconductor device, comprising:

• a first load terminal at a first side, a second load terminal and, coupled to the first load terminal and the second load terminal, a semiconductor body configured to conduct a load current between the first load terminal and the second load terminal and having a drift region of a first conductivity type;
• a plurality of trenches at the first side and extending into the semiconductor body along a vertical direction, wherein each trench includes a trench electrode insulated from the semiconductor body by a trench insulator, wherein two of the plurality of trenches are arranged laterally adjacent to each other and spatially confine a first type mesa, wherein the first type mesa is configured to conduct a part of the load current between the first load terminal and the drift region, wherein other two of the plurality of trenches are arranged laterally adjacent to each other and spatially confine a second type mesa configured to not conduct an inversion channel current, the second type mesa being arranged spatially separated from the first type mesa and electrically connected with the first load terminal, wherein a dummy mesa is laterally confined by yet other two of the plurality of trenches and arranged between two of the second type mesas, the dummy mesa being electrically insulated from the first load terminal and having a lateral width of at least 110% of the lateral width of the first type mesa;
• a source region of the first conductivity type in at least the first type mesa;
• a body region of a second conductivity type in at least the first type mesa, the body region separating the source region from the drift region.