Field effect transistor with isolation structure and method

A method, comprising:

• forming a first stack of nanostructures and a second stack of nanostructures;
• forming a sacrificial gate structure over the first and second stacks;
• forming a first source/drain region and a second source/drain region, the first source/drain region abutting the first stack, the second source/drain region abutting the second stack;
• forming a gate trench by removing the sacrificial gate structure;
• forming a wall structure in the gate trench;
• and
• forming a gate structure that wraps around the first and second stacks and abuts the wall structure, wherein upper surfaces of the gate structure and the wall structure are substantially coplanar.

A device, comprising:

• a first stack of nanostructures;
• a second stack of nanostructures horizontally offset from the first stack;
• a first source/drain region abutting the first stack of nanostructures;
• a second source/drain region abutting the second stack of nanostructures;
• a wall structure between the first and second stacks and spaced apart from the nanostructures of the first stack by first openings;
• a sidewall spacer that extends from the first stack to the second stack;
• and
• a first gate structure including a gate dielectric layer that wraps around the nanostructures of the first stack and merges in the first openings.