Semiconductor device including channel structure comprising different compositions

A semiconductor device comprising:

• a plurality of lower conductive lines extending in parallel on a substrate;
• a mold insulating pattern on the plurality of lower conductive lines, the mold insulating pattern defining a transistor region extending along a first lateral direction;
• a plurality of channel structures aligned along the first lateral direction in the transistor region, each of the plurality of channel structures comprising a vertical channel portion extending along a sidewall of the mold insulating pattern;
• an upper conductive line on the plurality of channel structures in the transistor region, the upper conductive line having a sidewall facing the vertical channel portion of each of the plurality of channel structures, the upper conductive line extending along the first lateral direction;
• a gate dielectric film between the plurality of channel structures and the upper conductive line;
• and
• a plurality of conductive contact patterns electrically connected to the vertical channel portions of the plurality of channel structures, respectively,
• wherein the vertical channel portions of the plurality of channel structures respectively comprise:
• a main channel portion in contact with a respective lower conductive line among the plurality of lower conductive lines, the main channel portion comprising an oxide semiconductor layer having a first composition;
• and
• a channel contact portion between the main channel portion and a respective conductive contact pattern among the plurality of conductive contact patterns, wherein the channel contact portion is in contact with the respective conductive contact pattern and comprises a material having a second composition that is different from the first composition.

A semiconductor device comprising:

• a peripheral circuit region on a substrate, the peripheral circuit region comprising a plurality of peripheral circuits;
• a lower conductive line on the peripheral circuit region, the lower conductive line being electrically connected to the plurality of peripheral circuits;
• a mold insulating pattern on the lower conductive line, the mold insulating pattern having a sidewall defining a transistor region;
• a channel structure in the transistor region, the channel structure comprising a bottom surface in contact with a top surface of the lower conductive line and a vertical channel portion adjacent the sidewall of the mold insulating pattern;
• a gate dielectric film on the channel structure in the transistor region;
• an upper conductive line on the gate dielectric film in the transistor region, the upper conductive line having a sidewall adjacent the vertical channel portion;
• and
• a conductive contact pattern electrically connected to the vertical channel portion,
• wherein the vertical channel portion of the channel structure comprises:
• a main channel portion spaced apart from the conductive contact pattern, the main channel portion comprising an oxide semiconductor layer having a first composition;
• and
• a channel contact portion in contact with the conductive contact pattern and comprising a material having a second composition that is different from the first composition.