Power field-effect transistor and manufacturing method

A method for manufacturing a power field-effect transistor comprising at least two source region at a top side of a semiconductor body, at least one drain region at a back side of the semiconductor body, at least two charge barrier regions in the semiconductor body so that electrically between each one of the source regions and the at least one drain region there is one of the charge barrier regions, and at least one gate electrode that is at least partially located in at least one trench in the semiconductor body, and the at least two charge barrier regions are located adjacent to the at least one trench, wherein, seen in the first plane, the at least one gate electrode comprises two electrically conductive wall regions located at trench walls of the at least one trench, wherein a trench bottom of the trench is partially free of the at least one gate electrode, and wherein, seen in the first plane, at least one of the following applies:

• a ratio of a width of the at least one trench to a depth of the at least one trench is between 0.6 and 1.8 inclusive, the width of the at least one trench is between 0.4 μm and 3 μm inclusive, a width of the at least two source regions is between 0.2 μm and 1.5 μm inclusive, a ratio of the width of the at least one trench to the width of the at least two source regions is between 5 and 0.8 inclusive, and a thickness of the at least two charge barrier regions is between 0.1 μm and 0.7 μm inclusive and wherein, next to the at least one trench and seen in a first plane perpendicular with the top side and perpendicular with a main elongation direction of the at least one trench, the top side of the semiconductor body is formed only by the at least two source regions, the method comprising:
• providing the semiconductor body comprising the at least two source regions, the at least one drain region and the at least two charge barrier regions,
• creating the at least one trench in the semiconductor body,
• producing the at least one gate electrode that is at least partially located in the at least one trench, wherein the at least one gate electrode comprises the two electrically conductive wall regions located at the trench walls of the at least one trench, and
• electrically connecting the at least two source regions and the at least two charge barrier regions.