Backside memory integration
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Wen Su, Jui-Lin Chen, Shih-Hao Lin, Ming-Yen Chuang, Chenchen Jacob Wang, Lien-Jung Hung, Ping-Wei Wang
Life of this patent
Estimating the term…
Abstract
Semiconductor structures and methods of the forming the same are provided. A semiconductor structure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.
Claims20
A semiconductor structure, comprising:
- a source feature and a drain feature disposed over and partially extending into a backside dielectric layer;
- an active region between the source feature and the drain feature;
- a gate structure over the active region;
- a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure;
- a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure;
- a storage element disposed in the backside interconnect structure;
- and
- a liner continuously and conformally extending from between a bottom surface of the source feature and the backside dielectric layer to between a bottom surface of the gate structure and the backside dielectric layer,
- wherein the liner interfaces the bottom surface of the gate structure.
A semiconductor structure, comprising:
- a first source feature and a second source feature disposed over a backside dielectric layer;
- a drain feature disposed between the first source feature and the second source feature;
- a first active region extending between the first source feature and the drain feature;
- a second active region extending between the drain feature and the second source feature;
- a first gate structure over the first active region;
- a second gate structure over the second active region;
- a contact etch stop layer (CESL) disposed on a top surface of the first source feature;
- an interlayer dielectric (ILD) layer over the CESL;
- a first source contact extending through the CESL and the ILD layer to couple to the first source feature;
- a backside interconnect structure disposed below the first source feature, the second source feature, the drain feature, the first gate structure, and the second gate structure;
- and
- a storage element disposed in the backside interconnect structure,
- wherein the backside interconnect structure is electrically coupled to the drain feature,
- wherein a bottom surface of the first source feature, a bottom surface of the second source feature, a bottom surface of the first gate structure, and a bottom surface of the second gate structure are spaced apart from the backside dielectric layer by a liner,
- wherein the liner is in direct contact with the bottom surfaces of the first gate structure and the second gate structure,
- wherein the liner comprises silicon nitride,
- wherein the backside interconnect structure directly interfaces a bottom surface of the backside dielectric layer away from the first gate structure and the second gate structure.
A semiconductor structure, comprising:
- a source feature and a drain feature disposed over and partially extending into a backside dielectric layer;
- an active region extending between the source feature and the drain feature;
- a gate structure over the active region;
- a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure;
- a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure;
- a storage element disposed in the backside interconnect structure;
- a backside contact extending from a bottom surface of the drain feature, through the backside dielectric layer, to engage the storage element;
- and
- a liner extending continuously and conformally along a bottom surface of the source feature, a bottom surface of the gate structure, and a sidewall of the backside contact,
- wherein the liner interfaces the bottom surface of the gate structure.
Dependencies are inferred from the claim text.