Method of fabricating transistors and stacked non-planar capacitors for memory and logic applications

A device, comprising:

• a first level comprising:
• a first electrode structure;
• a first plate electrode on the first electrode structure;
• a first plurality of plate capacitors on the first plate electrode, wherein the first plurality of plate capacitors comprises a first perovskite material;
• a first signal electrode on the first plate electrode, wherein the first signal electrode is between a first pair of plate capacitors in the first plurality of plate capacitors;
• a second level above the first level, the second level comprising:
• a second electrode structure coupled with the first signal electrode;
• a second plate electrode on the second electrode structure;
• a second plurality of plate capacitors on the second plate electrode, wherein the second plurality of plate capacitors comprise a second perovskite material;
• and
• a second signal electrode on the second plate electrode, wherein the second signal electrode is between a second pair of plate capacitors in the second plurality of plate capacitors;
• and
• a third level above the second level, the second level comprising:
• a third electrode structure coupled with the second signal electrode;
• a third plate electrode on the third electrode structure;
• and
• a third plurality of plate capacitors on the third plate electrode, wherein the third plurality of plate capacitors comprise a third perovskite material.