Ferroelectric tunnel junction structure with L-shaped spacers

A method of manufacturing a device, the method comprising:

• forming a ferroelectric tunnel junction (FTJ) including a bottom electrode, a top electrode, and a ferroelectric layer disposed between the bottom electrode and the top electrode, wherein a peripheral area of the ferroelectric layer is not covered by the top electrode and surrounds a sidewall of the top electrode;
• disposing a dielectric material in a space between the peripheral area of the ferroelectric layer and a sidewall of the top electrode;
• depositing at least one conformal metal oxide spacer including at least one of:
• prior to the disposing of the dielectric material, depositing an inner conformal metal oxide spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or
• after the disposing of the dielectric material, depositing an outer conformal metal oxide spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer;
• and
• annealing the FTJ to induce ferroelectric phase crystallization in the ferroelectric layer of the FTJ.

A method of manufacturing a device, the method comprising:

• forming a ferroelectric tunnel junction (FTJ) cell including bottom electrode, a ferroelectric layer disposed on the bottom electrode, and a top electrode disposed on the ferroelectric layer, wherein a peripheral area of the ferroelectric layer is not covered by the top electrode;
• disposing a conformal dielectric layer on a top and sidewall of the top electrode and on a surface of the peripheral area of the ferroelectric layer that is not covered by the top electrode;
• and
• annealing to induce ferroelectric phase crystallization in the ferroelectric layer;
• wherein a ratio of a coefficient of thermal expansion (CTE) of the conformal dielectric layer to a CTE of the ferroelectric layer is 0.67 or lower, and the portion of the conformal dielectric layer disposed on the surface of the peripheral area of the ferroelectric layer applies CTE difference-induced stress to the peripheral area of the ferroelectric layer during the annealing.