Memory device having vertical structure and memory system including the memory device

A non-volatile memory device comprising:

• a first lower semiconductor layer disposed below a first upper semiconductor layer including a first memory cell array, the first lower semiconductor layer overlapping with the first upper semiconductor layer in a vertical direction;
• and
• a second lower semiconductor layer disposed below a second upper semiconductor layer including a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction, the second lower semiconductor layer overlapping with the second upper semiconductor layer in a vertical direction,
• wherein the first lower semiconductor layer comprises:
• a first page buffer unit disposed in a second direction perpendicular to the first direction and electrically connected to the first memory cell array;
• a plurality of cache latches disposed in the second direction and spaced apart from the first page buffer unit in the first direction, and disposed at an edge of a portion of a second page buffer unit electrically connected to the second memory cell array to overlap with the first upper semiconductor layer in a vertical direction;
• and
• a first row decoder disposed adjacent to the first page buffer unit and the plurality of cache latches in the second direction and electrically connected to the first memory cell array.