US 12,593,451 B2Granted

Memory device, method of manufacturing memory device, and electronic device including memory device

AssigneeInstitute of Microelectronics, Chinese Academy of Sciences

InventorHuilong Zhu

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Abstract

Disclosed are a memory device, a method of manufacturing the memory device, and an electronic device. The memory device may include: a plurality of first device layers, each including first and second source/drain regions and a channel region; a plurality of second device layers stacked on the first device layers, each including third and fourth source/drain regions and a channel region; and a gate stack extending vertically to pass through the first and second device layers. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer, and a memory cell is defined at an intersection of the gate stack and each device layer. The gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.

Claims35

Dependent claims

A memory device, comprising:

a plurality of first device layers vertically stacked on a substrate, wherein each first device layer comprises a first source/drain region disposed at a lower vertical height in the first device layer, a second source/drain region disposed at an upper vertical height in the first device layer, and a channel region between the first source/drain region and the second source/drain region;
a plurality of second device layers vertically stacked on the plurality of first device layers, wherein each second device layer comprises a third source/drain region disposed at a lower vertical height in the second device layer, a fourth source/drain region disposed at an upper vertical height in the second device layer, and a channel region between the third source/drain region and the fourth source/drain region;
and
a gate stack extending vertically relative to the substrate to pass through the plurality of first device layers and the plurality of second device layers on the substrate, wherein the gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer of the plurality of first device layers and the plurality of second device layers, and a memory cell is defined at an intersection of the gate stack and each device layer,
wherein the gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.

2 more elements

A method of manufacturing a memory device, comprising:

disposing a first stack of a plurality of first device layers and a plurality of first sacrificial layers on a substrate, wherein each first device layer has a first sacrificial layer on at least a side of the first device layer;
forming a first processing channel extending vertically relative to the substrate to pass through the first stack based on a mask;
growing a seed layer continuously extending on the first stack by taking an uppermost first device layer in the first stack as a seed;
disposing a second stack of a plurality of second device layers and a plurality of second sacrificial layers on the seed layer, wherein each second device layer has a second sacrificial layer on at least a side of the second device layer;
forming a second processing channel extending vertically relative to the substrate to pass through the second stack based on the mask, wherein the second processing channel communicates with the first processing channel;
removing the first sacrificial layer through the first processing channel, and removing the second sacrificial layer through the second processing channel;
forming a first isolation layer in a space released due to a removal of the first sacrificial layer, through the first processing channel;
and forming a second isolation layer in a space released due to a removal of the second sacrificial layer, through the second processing channel;
and
forming a first gate stack in the first processing channel, wherein the first gate stack comprises a first gate conductor layer and a first memory functional layer disposed between the first gate conductor layer and the first device layer;
and forming a second gate stack in the second processing channel, wherein the second gate stack comprises a second gate conductor layer and a second memory functional layer disposed between the second gate conductor layer and the second device layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/547,391Filed 3 Apr 2023
Priority: CN 202310190808.X24 Feb 2023
Published: US 2024/0292618 A129 Aug 2024
Granted: 31 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/02
Erasable programmable read-only memories: electrically programmable
H10B 41/00
Electrically erasable-and-programmable rom [eeprom] devices comprising floating gates
H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…