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US 12,593,444 B2Granted
Method for manufacturing memory device having word line surrounding gate structure
AssigneeNanya Technology Corporation
InventorSzu-Yao Chang
Life of this patent
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Abstract
The present application provides a memory device having a word line (WL) surrounding a gate structure and a manufacturing method of the memory device. The memory device includes a first dielectric surrounding a capacitor; a second dielectric disposed over the first dielectric and the capacitor; a word line embedded in the second dielectric; and a gate structure disposed over the capacitor and extending through the second dielectric, wherein the gate structure is at least partially surrounded by the word line.
Claims15
A method of manufacturing a memory device, comprising:
- providing a first dielectric and a capacitor surrounded by the first dielectric;
- disposing a first dielectric layer, a conductive layer and a second dielectric layer sequentially over the first dielectric and the capacitor;
- forming a first trench extending through the second dielectric layer, the conductive layer and the first dielectric layer;
- disposing a sacrificial material within the first trench;
- removing the second dielectric layer;
- disposing a third dielectric layer conformal to the sacrificial material exposed through the conductive layer;
- disposing a patterned mask over the conductive layer, over the sacrificial material exposed through the conductive layer, and over the third dielectric layer surrounding the sacrificial material;
- removing portions of the conductive layer and the first dielectric layer exposed through the patterned mask to form a second trench;
- removing the patterned mask;
- disposing a fourth dielectric layer within the second trench;
- and
- removing the sacrificial material.
9 more elements
Dependencies are inferred from the claim text.