Semiconductor structure and manufacturing method thereof

A semiconductor structure, comprising:

• a base, wherein the base comprises a memory array region and a peripheral circuit region around the memory array region;
• a plurality of buried bit lines disposed in the memory array region of the base;
• and
• at least one buried gate disposed in the peripheral circuit region of the base;
• wherein the memory array region comprises a plurality of first active regions arranged in an array, each of the first active regions extends along a first direction, and the plurality of first active regions are isolated by using an isolation structure;
• the buried bit line comprises a bit line contact structure and a bit line conductive layer that are disposed sequentially;
• the bit line contact structure is connected to the first active region;
• and the bit line conductive layer is connected to the bit line contact structure;
• and
• the bit line conductive layer extends along a second direction in the memory array region and penetrates through a column of first active regions, and the second direction intersects the first direction non-perpendicularly.

A method of manufacturing a semiconductor structure, comprising:

• providing a base, wherein the base comprises a memory array region and a peripheral circuit region around the memory array region;
• and
• forming a plurality of buried bit lines in the memory array region, and forming at least one buried gate in the peripheral circuit region;
• wherein the memory array region comprises a plurality of first active regions arranged in an array, each of the first active regions extends along a first direction, and the plurality of first active regions are isolated by using an isolation structure;
• the peripheral circuit region comprises a second active region;
• and the forming a plurality of buried bit lines in the memory array region, and forming at least one buried gate in the peripheral circuit region comprises:
• forming a plurality of first trenches in the memory array region, wherein the plurality of first trenches are correspondingly arranged in the plurality of first active regions, and forming at least one gate trench in the peripheral circuit region, wherein the at least one gate trench penetrates through the second active region, and bottom surfaces of the plurality of first trenches are flush with a bottom surface of the at least one gate trench;
• and
• forming a plurality of second trenches in the memory array region, wherein each of the second trenches extends along a second direction, penetrates through a column of the first active regions, and communicates with the first trench formed in the column of the first active regions, a bottom surface of the second trench is higher than the bottom surface of the first trench, and the second direction intersects the first direction non-perpendicularly.