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US 12,593,442 B2Granted
Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Feng Kao, Katherine H. Chiang
Life of this patent
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Abstract
A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.
Claims20
A memory device, comprising:
- an insulating base including a trench and an upper surface;
- a transistor in the insulating base and including a vertical channel in the trench and a source electrode contacting a sidewall of the vertical channel, wherein the upper surface of the insulating base is substantially coplanar with an upper surface of the source electrode;
- an isolation layer in the trench on the transistor, wherein the isolation layer is on the upper surface of insulating base;
- and
- a capacitor comprising:
- a trench capacitor portion in the trench and separated from the transistor by the isolation layer;
- and
- a stacked capacitor portion outside the trench and contacting the source electrode of the transistor.
5 more elements
A memory device comprising:
- an insulating base including a trench;
- a first memory cell comprising:
- a first transistor in the insulating base and including a first vertical channel in the trench and a first source electrode contacting a sidewall of the first vertical channel;
- and
- a first capacitor including a first trench capacitor portion in the trench and a first stacked capacitor portion contacting the first source electrode outside the trench;
- a second memory cell comprising:
- a second transistor in the insulating base and including a second vertical channel in the trench and a second source electrode contacting the second vertical channel;
- and
- a second capacitor including a second trench capacitor portion in the trench and a second stacked capacitor portion contacting the second source electrode outside the trench;
- and
- an isolation layer in the trench and isolating the first transistor from the second transistor.
8 more elements
A memory device, comprising:
- a dielectric layer including a trench;
- a transistor in the dielectric layer including a vertical channel in the trench and a source electrode contacting a sidewall of the vertical channel;
- a capacitor comprising a trench capacitor portion in the trench and a stacked capacitor portion outside the trench and contacting the source electrode of the transistor;
- and
- an isolation layer in the trench between the transistor and the trench capacitor portion of the capacitor, wherein the isolation layer comprises a bottom portion contacting a bottom of the trench and the trench capacitor portion comprises:
- a lower conductive layer on a side of the isolation layer and separated from the transistor by the isolation layer;
- and
- a lower dielectric layer on a side of the lower conductive layer and contacting an upper surface of the bottom portion of the isolation layer.
5 more elements
Dependencies are inferred from the claim text.