US 12,593,438 B2Granted

Semiconductor memory devices

AssigneeSamsung Electronics Co., Ltd.

InventorsYangdoo Kim, Yonghwan Kim, Sangwuk Park, Sunghyun Park, Jinyoung Park, Minkyu Suh, Jungpyo Hong

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Abstract

A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

Claims18

Dependent claims

A semiconductor memory device comprising:

a substrate including a memory cell region;
a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode;
a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes;
a second support pattern located at a vertical level higher than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes;
and
a third support pattern contacting the sidewalls of the plurality of lower electrodes,
wherein the third support pattern is located at a vertical level higher than the vertical level of the second support pattern,
wherein the plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes,
wherein each recessed electrode portion of the plurality of recessed electrode portions has a first height which is the same as a vertical distance between an upper surface of the second support pattern and a lower surface of the third support pattern, and
wherein the upper electrode has a plurality of electrode protrusions protruding into a plurality of electrode recesses defined by the plurality of recessed electrode portions, respectively.

7 more elements

A semiconductor memory device comprising:

a substrate having a memory cell region;
a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, an upper electrode, and a capacitor dielectric layer between each of the plurality of lower electrodes and the upper electrode;
a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes;
a second support pattern contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes, wherein the second support pattern is located over the first support pattern, and located at a vertical level that is lower than uppermost ends of the plurality of lower electrodes and higher than middles of the plurality of lower electrodes in a vertical direction;
and
a third support pattern contacting the sidewalls of the plurality of lower electrodes and having an upper surface located at the same vertical level as the uppermost ends of the plurality of lower electrodes,
wherein each of the plurality of lower electrodes includes a recessed electrode portion protruding upward from an upper surface of the second support pattern and extending to a lower surface of the third support pattern, and
wherein the upper electrode surrounds the recessed electrode portion of each of the plurality of lower electrodes and includes an electrode protrusion extending toward the recessed electrode portion.

5 more elements

A semiconductor memory device comprising:

a substrate including a plurality of active regions arranged in a memory cell region;
a plurality of buried contacts connected to the plurality of active regions;
a plurality of landing pads arranged on the plurality of buried contacts;
a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes electrically connected to the plurality of landing pads, an upper electrode, and a capacitor dielectric layer located between each of the plurality of lower electrodes and the upper electrode;
a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes;
a second support pattern contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes, wherein the second support pattern is located over the first support pattern, and located at a vertical level that is lower than uppermost ends of the plurality of lower electrodes and higher than middles of the plurality of lower electrodes in a vertical direction;
and
a third support pattern contacting the sidewalls of the plurality of lower electrodes and being located over the second support pattern,
wherein each of the plurality of lower electrodes has a recessed electrode portion located between an upper surface of the second support pattern and a lower surface of the third support pattern,
wherein the recessed electrode portion is connected to the upper surface of the second support pattern and the lower surface of the third support pattern, and
wherein the upper electrode includes an electrode protrusion extending toward the recessed electrode portion of each of the plurality of lower electrodes.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/945,235Filed 15 Sep 2022
Priority: KR 10-2021-018428521 Dec 2021
Published: US 2023/0200053 A122 Jun 2023
Granted: 31 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells