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US 12,593,437 B2Granted
Semiconductor structure and method for forming the same
AssigneeFujian Jinhua Integrated Circuit Co., Ltd.
InventorsYi-Wang Jhan, Fu-Che Lee, Gang-Yi Lin, An-Chi Liu, Yifei Yan, Yu-Cheng Tung
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Abstract
A semiconductor structure includes a substrate, a contact structure disposed on the substrate, and two first gate structures disposed on the substrate and at two sides of the first contact structure. The contact structure has a T-shaped cross-sectional profile having a first portion contacting the substrate and a second portion disposed on the first portion. A top surface of the second portion of the contact structure is flush with top surfaces of the two first gate structures.
Claims7
A semiconductor structure, comprising:
- a substrate comprising a first region and a second region;
- two first gate structures disposed on the first region and a bit line disposed on the second region, wherein each of the first gate structures comprises a first electrode portion and a first hard mask portion disposed on the first electrode portion, the bit line comprises a second electrode portion and a second hard mask portion disposed on the second electrode portion, wherein an inner sidewall of the first hard mask portion locates on a top surface of the first electrode portion and the top surface of the first electrode portion is coplanar with a top surface of the second electrode portion;
- a first contact structure disposed on the substrate and between the two first gate structures, wherein the first contact structure has a T-shaped cross-sectional profile having a first portion contacting the substrate and a second portion disposed on the first portion, wherein a width of the second portion is larger than a width of the first portion, wherein a top surface of the second portion of the first contact structure is not higher than top surfaces of the hard mask portions of the two first gate structures, a bottom surface of the first portion is in direct contact with the substrate;
- two second contact structures disposed on the substrate at two sides of the-bit line, wherein top surfaces of the two second contact structures are higher than the top surface of the second portion of the first contact structure, bottom surfaces of the two second contact structures are in direct contact with the substrate and lower than the bottom surface of the first portion of the first contact structure;
- a passivation layer disposed on the second hard mask portion of the bit line, wherein the two second contact structures directly contact sidewalls of the passivation layer;
- and
- an interlayer dielectric layer disposed on the two first gate structures, the first contact structure, the two second contact structures, and the passivation layer.
4 more elements
Dependencies are inferred from the claim text.