Vertically stacked memory device and manufacturing method thereof

A manufacturing method of a vertical stack-type memory device comprising:

• forming a lower stack including a lower buffer layer, a first lower sacrificial layer, a first lower insulating layer, a second lower sacrificial layer, and a second lower insulating layer which are sequentially stacked;
• forming an insulating material layer on the lower stack;
• forming an upper stack including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer which are sequentially stacked on the insulating material layer;
• forming a first vertical hole penetrating through the upper stack, the insulating material layer, and the lower stack;
• forming a plurality of first recesses by removing portions of the first and second upper sacrificial layers, the first and second upper insulating layers, the first and second lower sacrificial layers, and the first and second lower insulating layers exposed by the first vertical hole;
• forming a plurality of second recesses by further removing portions of the first lower sacrificial layer and the second upper sacrificial layer exposed by the plurality of first recesses;
• forming a dielectric material layer on an inner surface of the first vertical hole including surfaces of the plurality of first and second recesses;
• forming a plurality of electrode members filling the plurality of second recesses on regions of the dielectric material layer formed in the plurality of second recesses;
• forming a channel material layer on the dielectric material layer and the electrode member exposed on the inner surface of the first vertical hole;
• forming a plurality of dielectric layer patterns from the dielectric material layer and forming a plurality of channel layer patterns from the channel material layer by removing portions of the dielectric material layer and the channel material layer which are disposed outside the first and second recesses;
• forming a body insulating layer which covers the plurality of channel layer patterns and the plurality of dielectric layer patterns and fills the first vertical hole;
• forming a second vertical hole penetrating through the body insulating layer and exposing one end of each of the plurality of channel layer patterns;
• forming a vertical bit line filling the second vertical hole;
• forming a first trench spaced apart from the vertical bit line and penetrating through the upper and lower stacks;
• forming a plurality of third recesses by removing the first upper sacrificial layer and the second lower sacrificial layer exposed by the first trench;
• forming a plurality of word lines filling the plurality of third recesses;
• exposing a portion of the plurality of dielectric layer patterns by removing the second upper sacrificial layer, the first lower sacrificial layer, the upper buffer layer, and the lower buffer layer;
• and
• forming a plurality of plate electrodes in contact with exposed portions of the plurality of dielectric layer patterns.

A vertical stack-type memory device comprising an upper memory cell, the upper memory cell comprising:

• a word line extending in a horizontal direction and having a vertical through-hole region;
• a vertical bit line arranged vertically to pass through the through-hole region;
• a channel layer pattern arranged to surround the vertical bit line inside the through-hole region, one end of which is connected to the vertical bit line and extending upward beyond an upper surface of the word line;
• a body insulating layer disposed between the vertical bit line and a remaining portion except for the one end of the channel layer pattern;
• an electrode member arranged to surround an outer peripheral surface of the channel layer pattern at a height higher than the word line;
• a dielectric layer pattern disposed between the word line and the channel layer pattern and having a structure surrounding the electrode member, one end of which is in contact with the vertical bit line and the other end of which is in contact with the other end of the channel layer pattern;
• and
• a plate electrode in contact with the dielectric layer pattern above the word line.