Semiconductor memory device of 2T-1C structure and method of fabricating the same

A semiconductor memory device, comprising:

• a first bit line and a second bit line extending in a first direction and spaced apart from each other in a second direction;
• a word line extending in the second direction on the first bit line and the second bit line;
• a capacitor on the word line, the capacitor including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode;
• a first channel pattern connecting the first bit line to the first electrode, the first channel pattern disposed adjacent to a side surface of the word line;
• and
• a second channel pattern connecting the second bit line to the second electrode, the second channel pattern disposed adjacent to an opposite side surface of the word line,
• the first channel pattern and the second channel pattern each including a first pattern portion overlapping the word line from below the word line, a second pattern portion adjacent to one of the side surface of the word line or the opposite side surface of the word line, and a third pattern portion extending from the second pattern portion, and
• the third pattern portion being horizontally offset from the first pattern portion,
• wherein a portion of the first channel pattern is between the word line and the first bit line, and a portion of the second channel pattern is between the word line and the second bit line.

A semiconductor memory device, comprising:

• a first bit line and a second bit line extending in a first direction and spaced apart from each other in a second direction;
• an interlayer insulating layer covering the first bit line and the second bit line, the interlayer insulating layer including a groove, the groove extending in the second direction and crossing both the first bit line and the second bit line;
• a first channel pattern connected to the first bit line, the first channel pattern in contact with a first inner side surface of the groove and covering a portion of a top surface of the interlayer insulating layer;
• a second channel pattern connected to the second bit line, the second channel pattern in contact with a second inner side surface of the groove, and the second channel pattern covering an other portion of the top surface of the interlayer insulating layer;
• a first bit line contact between the first channel pattern and the first bit line and connecting the first channel pattern and the first bit line to each other;
• a second bit line contact between the second channel pattern and the second bit line and connecting the second channel pattern and the second bit line to each other;
• a word line in the groove;
• a gate insulating layer between the word line and the first channel pattern and between the word line and the second channel pattern;
• a word line capping layer covering the word line;
• a first electrode on the interlayer insulating layer and in contact with the first channel pattern;
• a second electrode on the interlayer insulating layer and in contact with the second channel pattern;
• and
• a dielectric layer between the first electrode and the second electrode,
• the first channel pattern and the second channel pattern overlapping the first bit line and the second bit line, respectively.