Package substrate having embedded electronic component in a core of the package substrate

An electronic device, comprising:

• a package substrate comprising:
• a non-conductive core having an upper planar surface;
• a cavity extending at least partially through the upper planar surface of the non-conductive core to an interior planar surface of the non-conductive core, the cavity defined by a plurality of interior sidewalls of the non-conductive core extending from the interior planar surface of the non-conductive core to the upper planar surface of the non-conductive core;
• a deep trench capacitor (DTC) mounted in the cavity, wherein the DTC is a stand-alone capacitor die having a semiconductor body including an upper planar surface having one or more terminals, a lower planar surface, and a plurality of exterior sidewalls extending between the lower planar surface of the DTC and the upper planar surface of the DTC, wherein the lower planar surface of the DTC is supported by the interior planar surface of the non-conductive core via an adhesive layer so that the upper planar surface of the DTC is level with the upper planar surface of the non-conductive core;
• wherein the adhesive layer is disposed between the interior planar surface of the non-conductive core and the lower planar surface of the DTC, the adhesive layer extending along the interior planar surface of the non-conductive core beyond the plurality of exterior sidewalls of the DTC;
• and
• an upper metallization structure configured to provide one or more conductive paths from the one or more terminals of the DTC to one or more upper metal terminals of the upper metallization structure, wherein the adhesive layer isolates the semiconductor body and the plurality of exterior sidewalls of the DTC from electrical contact with the interior planar surface and the plurality of interior sidewalls of the cavity.

A method of forming a package substrate, comprising:

• forming a cavity extending from an upper planar surface of a non-conductive core to an interior planar surface of the non-conductive core, wherein the cavity is defined by a plurality of interior sidewalls of the non-conductive core extending from the interior planar surface of the non-conductive core to the upper planar surface of the non-conductive core;
• inserting a deep trench capacitor (DTC) in the cavity, wherein the DTC is a stand-alone capacitor die having a semiconductor body including an upper planar surface having one or more terminals, a lower planar surface, and a plurality of exterior sidewalls extending between the lower planar surface of the DTC and the upper planar surface of the DTC, wherein the lower planar surface of the DTC is supported via an adhesive layer by the interior planar surface of the non-conductive core so that the upper planar surface of the DTC is level with the upper planar surface of the non-conductive core;
• forming the adhesive layer between the interior planar surface of the non-conductive core and the lower planar surface of the DTC, the adhesive layer extending along the interior planar surface of the non-conductive core beyond the plurality of exterior sidewalls of the DTC;
• and
• forming an upper metallization structure over the upper planar surface of the non-conductive core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more terminals of the DTC to one or more upper metal terminals of the upper metallization structure, wherein the adhesive layer isolates the semiconductor body and the plurality of exterior sidewalls of the DTC from electrical contact with the interior planar surface and the plurality of interior sidewalls of the cavity.