Circuit board and semiconductor package comprising same
AssigneeLG Innotek Co., Ltd.
InventorsSe Woong Na, Sang Il Kim, Kee Han Lee
Life of this patent
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Abstract
A circuit board according to an embodiment includes an insulating layer; a circuit pattern layer including a first metal layer disposed on the insulating layer; a protective layer disposed on the insulating layer, vertically overlapping the first metal layer, and including a recess portion having a step in a horizontal direction; and a second metal layer disposed in the recess portion of the protective layer, wherein the recess portion includes a portion having a width greater than a width of the first metal layer, and wherein the second metal layer is disposed in the portion of the recess portion with a width greater than the width of the first metal layer.
Claims20
A circuit board comprising:
- an insulating layer;
- a circuit pattern layer including a first metal layer disposed on the insulating layer;
- a protective layer disposed on the insulating layer, vertically overlapping the first metal layer, and including a recess portion having a step in a horizontal direction;
- and
- a second metal layer disposed in the recess portion of the protective layer,
- wherein the recess portion includes a portion having a width greater than a width of the first metal layer, and
- wherein the second metal layer is disposed in the portion of the recess portion with a width greater than the width of the first metal layer,
- wherein the first metal layer includes a depression vertically overlapping the recess portion and concave toward the insulating laver, and
- wherein at least a portion of the second metal layer is disposed in the depression of the first metal laver.
A circuit board comprising:
- an insulating layer;
- a circuit pattern layer including a pad disposed on the insulating layer;
- a protective layer disposed on the insulating layer, vertically overlapping the pad and including a recess portion having different widths along a vertical direction;
- and
- a surface treatment layer disposed in the recess portion of the protective layer,
- wherein an upper surface of the surface treatment layer includes a region whose height decreases from a center of the recess portion toward an edge of the recess portion, and
- wherein at least a portion of a lower surface of the surface treatment layer is located lower than an upper surface of the pad.
A semiconductor package comprising:
- an insulating layer;
- a circuit pattern layer including a pad disposed on the insulating layer;
- a protective layer disposed on the insulating layer to overlap the pad in a vertical direction and including a recess portion having a step of different widths along the vertical direction;
- a metal layer disposed in the recess portion of the protective layer and having a step corresponding to the step of the recess portion;
- a connection part disposed on the metal layer;
- a chip mounted on the connection part;
- and
- a molding layer for molding the chip,
- wherein the recess portion includes:
- a first recess portion vertically overlapping the pad and having a first width;
- and
- a second recess portion vertically overlapping the first recess portion and having a second width greater than the first width,
- wherein the metal layer includes a first part disposed in the first recess portion and a second part disposed in the second recess portion, and
- wherein at least a portion of a lower surface of the metal layer is located lower than at least a portion of an upper surface of the pad.
Dependencies are inferred from the claim text.