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US 12,592,717 B2Granted
Integrator circuit
AssigneeNXP USA, Inc.
InventorsRonak Prakashchandra Trivedi, Hanqing Xing, Carmelo Morello, Ranga Seshu Paladugu
Life of this patent
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Abstract
The disclosure relates to an integrator circuit for a Sigma-Delta, ΣΔ, modulator, the integrator circuit comprising an integrator module comprising a differential amplifier, a sampling module comprising sampling capacitors and a reference module comprising first and second pluralities of reference capacitors connected between respective first and second lines and first and second pluralities of reference switches for connecting each of the reference capacitors to either a first reference terminal or a second reference terminal. In operation, the reference switches are switched according to a thermometrically coded quantizer signal.
Claims20
An integrator circuit for a Sigma-Delta (ΣΔ) modulator, the integrator circuit comprising:
- an integrator module comprising a differential amplifier having first and second inputs and first and second outputs, a first integrator capacitor connected between the first input and the first output, a second integrator capacitor connected between the second input and the second output;
- a first line switchably connected to the first input of the differential amplifier via a first switch and to the second input of the differential amplifier via a second switch;
- a second line switchably connected to the second input of the differential amplifier via a third switch and to the first input of the differential amplifier via a fourth switch;
- first and second sampling capacitors connected between the first line and respective fifth and sixth switches, the fifth switch connecting the first sampling capacitor to either a first common terminal or a first differential input terminal, the sixth switch connecting the second sampling capacitor to either the first common terminal or a second differential input terminal;
- third and fourth sampling capacitors connected between the second line and respective seventh and eighth switches, the seventh switch connecting the third sampling capacitor to either the first common terminal or the second differential input terminal, the eighth switch connecting the fourth sampling capacitor to either the first common terminal or the first differential input terminal;
- a first plurality of reference capacitors connected between the first line and a respective first plurality of reference switches, each of the first plurality of reference switches connecting a respective one of the first plurality of reference capacitors to either a first reference terminal or a second reference terminal;
- a second plurality of reference capacitors connected between the second line and a respective second plurality of reference switches, each of the second plurality of reference switches connecting a respective one of the second plurality of reference capacitors to either the first reference terminal or the second reference terminal;
- a ninth switch connected between a second common terminal and the first line;
- and
- a tenth switch connected between the second common terminal and the second line.
7 more elements
A method of operating an integrator circuit for a Sigma-Delta (ΣΔ) modulator, the integrator circuit comprising:
- an integrator module comprising a differential amplifier having first and second inputs and first and second outputs, a first integrator capacitor connected between the first input and the first output, a second integrator capacitor connected between the second input and the second output;
- a first line switchably connected to the first input of the differential amplifier via a first switch and to the second input of the differential amplifier via a second switch;
- a second line switchably connected to the second input of the differential amplifier via a third switch and to the first input of the differential amplifier via a fourth switch;
- first and second sampling capacitors connected between the first line and respective fifth and sixth switches, the fifth switch connecting the first sampling capacitor to either a first common terminal or a first differential input terminal, the sixth switch connecting the second sampling capacitor to either the first common terminal or a second differential input terminal;
- third and fourth sampling capacitors connected between the second line and respective seventh and eighth switches, the seventh switch connecting the third sampling capacitor to either the first common terminal or the second differential input terminal, the eighth switch connecting the fourth sampling capacitor to either the first common terminal or the first differential input terminal;
- a first plurality of reference capacitors connected between the first line and a respective first plurality of reference switches, each of the first plurality of reference switches connecting a respective one of the first plurality of reference capacitors to either a first reference terminal or a second reference terminal;
- a second plurality of reference capacitors connected between the second line and a respective second plurality of reference switches, each of the second plurality of reference switches connecting a respective one of the second plurality of reference capacitors to either the first reference terminal or the second reference terminal;
- a ninth switch connected between a second common terminal and the first line;
- and
- a tenth switch connected between the second common terminal and the second line, the method comprising in sequence:
- in a first sampling phase:
- providing a first clock signal to close the ninth and tenth switches;
- providing a first switching signal to operate the fifth, sixth, seventh and eighth switches to connect the first sampling capacitor to the first common terminal, the second sampling capacitor to the second differential input terminal, the third sampling capacitor to the first common terminal and the fourth capacitor to the first differential input terminal;
- providing a thermometrically coded quantizer signal to operate the reference switches, connecting each of the first and second plurality of reference capacitors to either the first or second reference terminals;
- in a first integration phase:
- opening the ninth and tenth switches;
- and
- providing a second switching signal and a second clock signal to close the second and fourth switches.
15 more elements
Dependencies are inferred from the claim text.