Adaptive power tuning in a successive approximation analog-to-digital converter

A Successive Approximation Analog-to-Digital Converter (SAR_ADC) comprising:

• a comparator having a first input operable to receive an input voltage (VIN), and a second input coupled to a capacitive digital-to-analog converter (DAC) to receive a DAC voltage (VDAC), the comparator operable to compare VIN to the VDAC from the DAC;
• a Successive Approximation Register (SAR) coupled to a comparator output, the SAR operable to provide digital-signals to the DAC, and to store and output a n-bit binary-number approximating VIN;
• and
• a reference buffer coupled to and controlled by the SAR to provide a reference voltage (VREF) to the DAC,
• wherein the DAC comprises a plurality of capacitances, each including a first terminal coupled to a DAC output node and a second terminal coupled through a switch controlled by one of the digital-signals to a VIN node, a VREF node or ground, the DAC operable to sequentially drive each of the capacitances beginning with that representing a most significant bit (MSB) of the n-bit binary-number towards VREF, and
• wherein the comparator comprises a pre-amplifier coupled to the first input and second input and a set-reset (SR) latch coupled between a pre-amplifier output and the comparator output, and further comprising a variable-capacitance element coupled to the pre-amplifier output, the variable-capacitance element operable to dynamically adjust an output capacitance of the pre-amplifier based on a bit of the n-bit binary-number represented by the capacitance being driven by the DAC and compared by the comparator.

A method of operating an Analog-to-Digital Converter including a comparator, a digital-to-analog converter (DAC) and a Successive Approximation Register (SAR) to output an n-bit binary-number approximating an analog input voltage (VIN) to the converter, the method comprising:

• coupling a first input of the comparator to VIN and a second input to first terminals of each of a plurality of capacitances in the DAC;
• coupling first terminals of each of the capacitances to ground and second terminals of the capacitances to VIN to trap a charge proportional to VIN on the capacitances;
• decoupling the first terminals of the capacitances from ground and switching the second terminals from VIN to ground driving a voltage (VDAC) on the first terminals to a negative VIN;
• beginning with a capacitance of the capacitances representing a most significant bit (MSB) of the n-bit binary-number:
• driving the VDAC on the first terminal of the capacitance in a positive direction by switching the second terminal from ground to a reference voltage (VREF) from a reference buffer;
• comparing the VDAC coupled to the second input from the capacitance being driven to the VIN coupled to the first input, and:
• if VIN is >VDAC outputting from the comparator to the SAR a logic 1, signaling a switch coupling the second terminal of the capacitance being driven to remain closed, and setting the MSB of the n-bit binary-number as logic 1;
• and
• if VIN is <VDAC outputting from the comparator a logic 0, signaling the switch to couple the second terminal to ground, and resetting the MSB of the n-bit binary-number as logic 0;
• and
• repeating driving the VDAC and comparing VDAC to VIN for the of each capacitances sequentially from a capacitance representing a second most significant bit (MSB−1) of the n-bit binary-number to that representing a least significant bit (LSB),
• wherein driving the capacitance comprises dynamically tuning a drive-strength of the reference buffer based a bit of the n-bit binary-number represented by the capacitance being driven.