Post-sampling selectable gain in sample and hold analog-to-digital converters
AssigneeInfineon Technologies Americas Corp.
InventorsDavid Schaffenrath, Rocco Calabro, Ketan Dewan
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AssigneeInfineon Technologies Americas Corp.
InventorsDavid Schaffenrath, Rocco Calabro, Ketan Dewan
Estimating the term…
A system and method for a post-sampling selectable gain circuit in sample and hold (S/H) analog-to-digital converters (ADCs). The method includes scaling down or scaling up a reference voltage to generate a plurality of candidate voltages associated with a plurality of measurement accuracies of a sampler circuit, each candidate voltage of the plurality of candidate voltages is respectively associated with a respective measurement accuracy of the plurality of measurement accuracies. The method includes selecting, by a processing device and based on an input voltage for the sampler circuit, a particular candidate voltage from the plurality of candidate voltages that is associated with an optimal measurement accuracy of the plurality of measurement accuracies. The method includes generating a sampler voltage associated with the optimal measurement accuracy by operating the sampler circuit based on the particular candidate voltage or an additional voltage associated with the particular candidate voltage.
A method comprising:
An integrated circuit, comprising:
A method comprising:
Dependencies are inferred from the claim text.