SAR analog-to-digital converter with high-order noise-shaping characteristics

A successive approximation register (SAR) analog-to-digital converter comprising:

• an input unit including at least one SAR capacitor;
• a recycling integrator connected to the input unit and including k integration capacitors configured to store respective residue information generated in an integration process performed k times, respectively, (where k denotes a positive integer of 2 or more) using a single amplifier;
• a comparator connected to an output terminal of the recycling integrator;
• and
• a SAR controller connected to an output terminal of the comparator and configured to generate a digital signal corresponding to output of the comparator, wherein the input unit is configured to store an input voltage received through an (n−1)-th (where n denotes a positive integer of 2 or more) sampling process in the SAR capacitor as an (n−1)-th input signal,
• wherein the recycling integrator is configured to store residue information generated in a first integration process in a first integration capacitor, to store residue information generated in a second integration process in a second integration capacitor, and to connect in series the SAR capacitor, the first integration capacitor, and the second integration capacitor before an n-th SAR conversion process corresponding to an n-th sampling process is performed, and to reduce input of the comparator to one, and
• wherein the recycling integrator is further configured to,
• in the first integration process, connect the SAR capacitor to the first integration capacitor and a common integration capacitor and store the (n−1)-th input signal in each of the first integration capacitor and the common integration capacitor as residue information generated in the first integration process, and
• in the second integration process, connect the common integration capacitor and the second integration capacitor and store the residue information stored in the common integration capacitor in the second integration capacitor as residue information generated in the second integration process.