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US 12,592,707 B2Granted
Circuits for online adaptive DC offset correction and receivers
AssigneeChongqing GigaChip Technology Co., Ltd.
InventorsYouhua Wang, Fei Li, Kairang Chen, Dongbing Fu, Can Zhu
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Abstract
Embodiments of the disclosure provide a circuit for online adaptive direct current offset correction, which includes: an analog adder circuit, a digital-to-analog conversion circuit, a direct current detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit. Embodiments of the present disclosure also provide a zero-IF receiver including a circuit for online adaptive DC offset correction.
Claims14
A circuit for online adaptive DC offset correction, applied to a zero-IF receiver, comprising:
- an analog adder circuit configured to receive a first input signal generated by the zero-IF receiver and a second input signal generated by a digital-to-analog conversion circuit, and generate a first output signal according to the first input signal and the second input signal;
- an analog-to-digital conversion circuit configured to receive the first output signal and perform analog-to-digital conversion on the first output signal to obtain a second output signal;
- a DC detection circuit configured to perform DC detection on the second output signal under a control of a detection control signal generated by an adaptive update signal generating circuit to generate a detection result, and the DC detection circuit comprising:
- a delay sub-circuit configured to receive the second output signal and perform delay processing on the second output signal to generate a delayed signal;
- a digital adder sub-circuit configured to receive the delay signal and perform an addition operation on the second output signal and an output signal of the delay sub-circuit to generate an addition signal;
- a divider sub-circuit configured to receive the addition signal and perform division operation on the addition signal;
- and
- an accumulator sub-circuit configured to receive the division signal and the update control signal and generate a detection result according to the division signal and the update control signal;
- the adaptive update signal generating circuit configured to receive the detection result and generate an update control signal according to the detection result;
- an output circuit configured to receive the update control signal and generate a first mode selection signal according to the update control signal;
- and
- a mode selection circuit configured to receive the first mode selection signal and generate a correction signal according to the first mode selection signal and a second mode selection signal, wherein the correction signal is used as an input signal of the digital-to-analog conversion circuit.
9 more elements
A zero-IF receiver, comprising a circuit for online adaptive DC offset correction, wherein the circuit includes:
- an analog adder circuit configured to receive a first input signal generated by the zero-IF receiver and a second input signal generated by a digital-to-analog conversion circuit, and generate a first output signal according to the first input signal and the second input signal;
- an analog-to-digital conversion circuit configured to receive the first output signal and perform analog-to-digital conversion on the first output signal to obtain a second output signal;
- a DC detection circuit configured to perform DC detection on the second output signal under a control of a detection control signal generated by an adaptive update signal generating circuit to generate a detection result, and comprising:
- a delay sub-circuit configured to receive the second output signal and perform delay processing on the second output signal to generate a delayed signal;
- a digital adder sub-circuit configured to receive the delay signal and perform an addition operation on the second output signal and an output signal of the delay sub-circuit to generate an addition signal;
- a divider sub-circuit configured to receive the addition signal and perform division operation on the addition signal;
- and
- an accumulator sub-circuit configured to receive the division signal and the update control signal and generate a detection result according to the division signal and the update control signal;
- the adaptive update signal generating circuit configured to receive the detection result and generate an update control signal according to the detection result;
- an output circuit configured to receive the update control signal and generate a first mode selection signal according to the update control signal;
- and
- a mode selection circuit configured to receive the first mode selection signal and generate a correction signal according to the first mode selection signal and a second mode selection signal, wherein the correction signal is used as an input signal of the digital-to-analog conversion circuit.
9 more elements
Dependencies are inferred from the claim text.