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US 12,592,704 B2Granted
TD converter, PLL circuit, TD converting method, and clock generating method
AssigneeAsahi Kasei Microdevices Corporation
InventorTakeji Fujibayashi
Life of this patent
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Abstract
Provided is a TD converter including: a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock; and a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively.
Claims21
A TD converter comprising:
- a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock;
- and
- a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively;
- wherein each of the first oscillator and the second oscillator is configured to be operable in at least two operating modes including a high speed operating mode and a low speed operating mode, the oscillation frequency of which is lower than that of the high speed operating mode.
1 more element
A TD converting method comprising:
- by a first oscillator and a second oscillator of a plurality of oscillators, receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock;
- and
- by a computation circuit, calculating a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively;
- wherein each of the first oscillator and the second oscillator is configured to be operable in at least two operating modes including a high speed operating mode and a low speed operating mode, the oscillation frequency of which is lower than that of the high speed operating mode.
1 more element
A clock generating method comprising:
- by a first oscillator and a second oscillator of a plurality of oscillators, receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock;
- by a computation circuit, calculating a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively;
- and
- outputting an output clock with a frequency depending on the digital output value, wherein
- the plurality of oscillators receive a feedback clock depending on the output clock input thereto as the target clock;
- wherein each of the first oscillator and the second oscillator is configured to be operable in at least two operating modes including a high speed operating mode and a low speed operating mode, the oscillation frequency of which is lower than that of the high speed operating mode.
3 more elements
A TD converter comprising:
- a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock;
- and
- a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively;
- wherein each of the plurality of oscillators includes a ring oscillator formed by delay elements cascaded in a ring shape;
- and
- wherein each of the first oscillator and the second oscillator is configured to enable switch of the operating mode by switching a delay time in the delay element in accordance with the control signal.
3 more elements
A TD converter comprising:
- a plurality of oscillators which at least include a first oscillator and a second oscillator receiving control signals input thereto, respectively, and operating in operating modes with oscillation frequencies different from each other, respectively, wherein each control signal indicates a time difference between a reference clock and a target clock;
- and
- a computation circuit which calculates a digital output value depending on the time difference, by using a plurality of pieces of phase information retained according to the reference clock in the plurality of oscillators, respectively;
- wherein each of the plurality of oscillators includes a ring oscillator formed by delay elements cascaded in a ring shape;
- and
- wherein each of the plurality of pieces of phase information includes circulation count information which indicates a circulation count of the ring oscillator, and position information which indicates a position of the delay element at which a logic level of an input is equal to a logic level of an output.
3 more elements
Dependencies are inferred from the claim text.