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US 12,592,701 B2Granted
Level shifter and semiconductor device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsEonguk Kim, Jinsu Jeong, Chanhee Jeon
Life of this patent
Estimating the term…
Abstract
A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.
Claims12
A level shifter, comprising:
- a first stage including a plurality of first elements, the first stage being configured to receive a reference voltage and comprising a first power supply configured to provide a first voltage higher than the reference voltage;
- a second stage including a plurality of second elements, the second stage being configured to receive the first voltage and comprising a second power supply configured to provide a second voltage higher than the first voltage;
- and
- a third stage including a plurality of third elements, the third stage being configured to receive the second voltage and comprising a third power supply configured to provide a third voltage higher than the second voltage,
- wherein a difference between the reference voltage and the first voltage, a difference between the first voltage and the second voltage, and a difference between the second voltage and the third voltage are equal to each other,
- wherein the first stage is configured to receive an input signal swinging back and forth from the reference voltage to the first voltage and to output a first output signal to the second stage,
- wherein the second stage is configured to receive, at a gate of at least one second element of the plurality of second elements, the first output signal from the first stage, and output a second output signal swinging between the first voltage and the second voltage,
- wherein the plurality of second elements comprises a negative-channel metal-oxide semiconductor (NMOS) transistor that is configured to receive, at a gate of the NMOS transistor, the second output signal,
- wherein the at least one second element of the plurality of second elements is a positive-channel metal-oxide semiconductor (PMOS) transistor, and
- wherein the third stage is configured to output a third output signal swinging between the second voltage and the third voltage.
7 more elements
A level shifter, comprising:
- an input circuit comprising a first power supply configured to provide a first voltage, wherein the input circuit is configured to receive an input signal swinging back and forth from a reference voltage to the first voltage, wherein the first voltage is greater than the reference voltage;
- an output circuit configured to output a first output signal that swings between a second voltage, which is greater than the first voltage, and a third voltage, which is greater than the second voltage;
- and
- a tolerant circuit comprising a plurality of elements and connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second voltage,
- wherein the input circuit is configured to output a second output signal to the tolerant circuit,
- wherein the tolerant circuit is configured to output a tolerant output signal to the output circuit,
- wherein the tolerant circuit is configured to receive, at a gate of at least one element of the plurality of elements, the second output signal from the input circuit,
- wherein the plurality of elements further comprises a negative-channel metal-oxide semiconductor (NMOS) transistor that is configured to receive, at a gate of the NMOS transistor, the tolerant output signal,
- wherein at least one element of the plurality of elements is a positive-channel metal-oxide semiconductor (PMOS) transistor, and
- wherein a difference between the reference voltage and the first voltage, a difference between the first voltage and the second voltage, and a difference between the second voltage and the third voltage are equal to each other.
7 more elements
Dependencies are inferred from the claim text.