Phase interpolator (PI) including weighted summing circuit and related methods

A method in a weighted summing phase interpolator (PI) circuit, the method comprising:

• generating, in a first PI circuit, a first interpolated clock having a first interpolated phase in response to a first interpolation code;
• generating, in a second PI circuit, a second interpolated clock having a second interpolated phase in response to a second interpolation code;
• generating, in a weighted summing circuit and based on a weight signal, a third interpolated clock at a third interpolated phase between the first interpolated phase and the second interpolated phase, wherein the weighted summing circuit further comprises a weight calibration circuit;
• determining, in the weight calibration circuit, a first time period between an early phase of the third interpolated clock based on a minimum interpolation code and a late phase of the third interpolated clock based on a maximum interpolation code;
• determining, in the weight calibration circuit, a second time period between the early phase and a test phase of the third interpolated clock in response to a middle interpolation code in a first test period of a first reference clock;
• determining, in the weight calibration circuit, a third time period between the early phase and the test phase of the third interpolated clock in response to the middle interpolation code in a second test period of the first reference clock;
• and
• incrementing, by the weight calibration circuit, the weight signal in response to determining a sum of the second time period and the third time period is greater than the first time period.

An integrated circuit (IC) comprising:

• a sequential logic circuit configured to store data in response to a system clock;
• a capture circuit configured to, in each cycle of the system clock, receive the data from the sequential logic circuit in response to a third interpolated clock;
• and
• a weighted summing phase interpolator (PI), comprising:
• a first PI circuit configured to generate a first interpolated clock having a first interpolated phase in response to a first interpolation code;
• a second PI circuit configured to generate a second interpolated clock having a second interpolated phase in response to a second interpolation code;
• a weighted summing circuit configured to employ a weight signal to generate the third interpolated clock at a third interpolated phase, based on the weight signal, between the first interpolated phase and the second interpolated phase, wherein the weighted summing circuit further comprises a weight calibration circuit, the weight calibration circuit configured to:
• determine a first time period between an early phase of the third interpolated clock based on a minimum interpolation code and a late phase of the third interpolated clock based on a maximum interpolation code;
• determine a second time period between the early phase and a test phase of the third interpolated clock in response to a middle interpolation code in a first test period of a first reference clock;
• determine a third time period between the early phase and the test phase of the third interpolated clock in response to the middle interpolation code in a second test period of the first reference clock;
• and
• increment the weight signal in response to determining a sum of the second time period and the third time period is greater than the first time period.