Flip-flops and integrated circuits including the same

A flip-flop comprising:

• a first p-channel metal-oxide semiconductor (PMOS) transistor that includes a source coupled to a power supply voltage and a gate configured to receive a data input signal;
• a second PMOS transistor that is connected between the first PMOS transistor and a first node, wherein the second PMOS transistor includes a gate configured to receive a clock signal;
• a first n-channel metal-oxide semiconductor (NMOS) transistor that is connected between the first node and a ground voltage, wherein the first NMOS transistor includes a gate configured to receive the data input signal;
• a third PMOS transistor that is connected between a second node and a third node, wherein the third PMOS transistor includes a gate configured to receive the clock signal;
• a second NMOS transistor that includes a drain coupled to the second node and a gate coupled to the first node;
• a third NMOS transistor that is connected between the second NMOS transistor and the ground voltage, wherein the third NMOS transistor includes a gate configured to receive the clock signal;
• a first inverter configured to output a first inverted signal by inverting a first signal of the first node;
• a fourth PMOS transistor that is connected between the power supply voltage and a fourth node, wherein the fourth PMOS transistor includes a gate coupled to the second node;
• a fourth NMOS transistor that includes a drain coupled to the fourth node and a gate configured to receive the clock signal;
• a fifth NMOS transistor that includes a drain coupled to the fourth NMOS transistor and a gate configured to receive the first inverted signal;
• a sixth NMOS transistor that is connected between the fifth NMOS transistor and the ground voltage, wherein the sixth NMOS transistor includes a gate coupled to the second node;
• a second inverter configured to provide an output signal by inverting an inverted output signal of the fourth node;
• a fifth PMOS transistor that is connected between the power supply voltage and the third node, wherein the fifth PMOS transistor includes a gate configured to receive the first signal;
• and
• a sixth PMOS transistor that is connected between the power supply voltage and the third node in parallel with the fifth PMOS transistor, wherein the sixth PMOS transistor includes a gate configured to receive the inverted output signal.

An integrated circuit comprising:

• a clock generator configured to generate a clock signal having a true single phase;
• and
• a plurality of flip-flops connected in series and configured to operate based on the clock signal,
• wherein each of the plurality of flip-flops includes:
• a first precharge circuit connected between a power supply voltage and a first node, the first precharge circuit configured to selectively charge the first node based on a data input signal and the clock signal;
• a first discharge circuit connected between the first node and a ground voltage, the first discharge circuit configured to selectively discharge the first node based on the data input signal;
• a first inverter configured to output a first inverted signal by inverting a first signal of the first node;
• a switching circuit configured to selectively connect a second node and a third node based on the clock signal;
• a second discharge circuit connected between the second node and the ground voltage, the second discharge circuit configured to selectively discharge the second node based on the clock signal;
• a second precharge circuit connected between the power supply voltage and a fourth node, the second precharge circuit configured to selectively charge the fourth node based on a second signal of the second node;
• a third discharge circuit connected between the fourth node and the ground voltage, the third discharge circuit configured to selectively discharge the fourth node based on the clock signal, the first inverted signal, and the second signal;
• a second inverter configured to provide an output signal by inverting an inverted output signal of the fourth node;
• a switching prevention circuit connected between the power supply voltage, the switching prevention circuit configured to prevent, based on the first signal, a switching of a voltage level of the second node in response to a toggling of the clock signal;
• a first a retention strengthening circuit connected between the power supply voltage and the third node in parallel with the switching prevention circuit, the first retention strengthening circuit configured to maintain a logic level of the second signal based on the inverted output signal;
• and
• a second retention strengthening circuit connected between the first node and a fifth node in the second discharge circuit, the second retention strengthening circuit configured to maintain a logic level of the first node based on the first inverted signal.