Off-state isolation bias circuit for D-mode amplifiers

A circuit, comprising:

• a first amplifier comprising a first output transistor, the first output transistor comprising a first source electrode, a first drain electrode, and a first gate electrode;
• and
• a bias circuit in operable communication with the first amplifier, the bias circuit comprising:
• a first control loop configured to set a first quiescent bias for the first output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to put the first output transistor in an “on” state;
• a second control loop configured to set a second quiescent bias for the first output transistor based on the first value of the first control voltage and the second value of the second control voltage, wherein the second quiescent bias is configured to put the first output transistor in an “off” state and to increase an insertion loss of the first amplifier when the first output transistor is in the “off” state;
• and
• a first level shifting network having a first terminal coupled to a node common to the first control loop and the second control loop and a second control terminal coupled to the first gate electrode, the first level shifting network being shared by the first control loop and the second control loop and configured to level shift a signal provided to the first gate electrode.