Amplifier for a radio frequency receiver

An amplifier comprising:

• a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential;
• a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor;
• a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential, the second power supply potential being a ground;
• and
• a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element comprising a switched capacitor comprising:
• a first switch connected to the gate of the first MOS transistor and to a first electrode of a third capacitive element;
• a second switch connected to a second electrode of the third capacitive element and to the drain of the first MOS transistor;
• a third switch connected to the first electrode of the third capacitive element and to a third node configured to receive a first bias potential;
• and
• a fourth switch connected to the second electrode of the third capacitive element and to a fourth node configured to receive a second bias potential.

An amplifier comprising:

• a first MOS transistor having a source coupled to a first node configured to receive a first power supply potential;
• a second MOS transistor having a source coupled to a second node configured to receive a second power supply potential,
• wherein drains of the first and second MOS transistors are connected together and to an output of the amplifier;
• a first resistive element and a first capacitive element connected in parallel between a gate and the drain of the first MOS transistor, the first resistive element comprising a first switched capacitor comprising:
• a first switch connected between the gate of the first MOS transistor and a first electrode of a second capacitive element;
• a second switch connected between a second electrode of the second capacitive element and the drain of the first MOS transistor;
• a third switch connected between the first electrode of the second capacitive element and a third node configured to receive a first bias potential;
• and
• a fourth switch connected between the second electrode of the second capacitive element and a fourth node configured to receive a second bias potential;
• and
• a third resistive element and a third capacitive element connected in parallel between a gate and the drain of the second MOS transistor, the third resistive element comprising a second switched capacitor comprising:
• a fifth switch connected between the gate of the second MOS transistor and a first electrode of a fourth capacitive element;
• a sixth switch connected between a second electrode of the fourth capacitive element and the drain of the second MOS transistor;
• a seventh switch connected between the first electrode of the fourth capacitive element and a fifth node configured to receive a third bias potential;
• and
• an eighth switch connected between the second electrode of the fourth capacitive element and the fourth node.