# US 12,592,294 B2 · Apparatuses, systems, and methods for storing error information and providing recommendations based on same

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- Number: US 12,592,294 B2
- Document ID: US12592294B2
- Status: Granted
- Kind: B2
- Application number: 18/598,937
- Filed: 2024-03-07
- Published: 2024-09-19
- Granted: 2026-03-31
- Earliest claimed: 2023-03-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sujeet Ayyapureddi
- Web page: https://patentgrep.com/patent/US12592294B2

## CPC

- G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0409: {Online test}
- G11C 2029/1202: {Word line control}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.

## Claims

### Claim 1

An apparatus comprising:
a memory array comprising a plurality of word lines configured to store a plurality of code words;
a mode register;
an error correction code (ECC) circuit configured to detect and correct errors in the plurality of code words;
an error correction and scrub (ECS) circuit configured to:
receive an active detection signal from the ECC circuit when the ECC circuit detects an error in a code word of the plurality of code words of a word line of the plurality of word lines and update a value indicative of a number of code words of the plurality of code words with errors for the word line; and
analyze the value and provide to the mode register a row address associated with the word line based on the analysis, wherein the mode register is configured to store the row address.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the mode register is configured to provide the row address to a controller responsive to a mode register read command.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising an external pin, wherein the mode register is configured to provide an active alert signal to the external pin based on receiving the row address from the ECS circuit.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising an external pin, wherein the ECS circuit is configured to provide an active alert signal to the external pin based on the analysis.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising a fuse array configured to store baseline error information, wherein the ECS circuit is further configured to analyze the value and the baseline error information.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the ECS circuit is further configured to analyze a plurality of values, wherein each of the plurality of values indicate the number of code words of the plurality of code words with errors for the word line, wherein the value is one of the plurality of values.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the ECS circuit causes the value to be written to the memory array.