Efuse unit and application circuit thereof
AssigneeShanghai Huali Integrated Circuit Corporation
InventorYing Yan
Life of this patent
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Abstract
The present invention discloses an efuse unit, including a first fuse, a second fuse, a first NMOS, a second NMOS and a third NMOS. One end of the first fuse serves as a Q1 port, and the other end is connected to drain end of the third NMOS and the first NMOS. One end of the second fuse serves as a Q2 port and is short-circuited to a source end of the third NMOS, and the other end is connected to a drain end of the second NMOS. Agate end of the third NMOS serves as an RDWL port. A gate end of the first NMONS serves as a WLC port. A gate end of the second NMOS serves as a WL port. The present invention can improve the correctness of the reading operation, reduce the voltage required for the programming operation, reduce the programming current.
Claims6
An application circuit of an efuse unit, comprising:
- a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor (Mp1), a second PMOS transistor (Mp2) and a Sense Amplifier (SA) module;
- the efuse unit, comprising a first fuse (link1), a second fuse (link2), a first N-channel Metal-Oxide Semiconductor (NMOS) transistor (Mn1), a second NMOS transistor (Mn2) and a third NMOS transistor (Mn3);
- one end of the first fuse (link1) serving as a Q1 port of the efuse unit, and the other end being connected to a drain end of the third NMOS transistor (Mn3) and a drain end of the first NMOS transistor (Mn1);
- one end of the second fuse (link2) serving as a Q2 port of the efuse unit and being short-circuited to a source end of the third NMOS transistor (Mn3), and the other end being connected to a drain end of the second NMOS transistor (Mn2);
- a source end of the first NMOS transistor (Mn1) and a source end of the second NMOS transistor (Mn2) being connected to the ground;
- a gate end of the third NMOS transistor (Mn3) serving as a reading operation control signal (RDWL) port of the efuse unit;
- a gate end of the first NMOS transistor (Mn1) serving as a work line control (WLC) port of the efuse unit;
- and a gate end of the second NMOS transistor (Mn2) serving as a word line (WL) port of the efuse unit;
- a drain end (BLA) of the first PMOS transistor (Mp1) being connected to the Q1 port of the efuse unit;
- a drain end (BLB) of the second PMOS transistor (Mp2) being connected to the Q2 port of the efuse unit;
- source ends of the first PMOS transistor (Mp1) and the second PMOS transistor (Mp2) being short-circuited to a programming power supply (VDDQ);
- gate ends of the first PMOS transistor (Mp1) and the second PMOS transistor (Mp2) being short-circuited to a bit line control signal (BLC);
- and
- the Q1 port of the efuse unit being connected to the SA module.
Dependencies are inferred from the claim text.