Non-volatile memory with in-place error updating and correction

A method comprising:

• reading a data set from a plurality of non-volatile memory cells in overlapping threshold voltages distributions, the plurality of non-volatile memory cells are arranged in NAND strings, each of the NAND string including a Gate Induced Drain Leakage (“GIDL”) transistor;
• determining that the data set was not read successfully;
• and
• in response to determining that the data set was not read successfully:
• identifying memory cells storing error bits by identifying memory cells in threshold voltage overlap regions between neighboring overlapping threshold voltages distributions;
• determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages in upper tails by determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages above a respective demarcation voltage within the overlap regions;
• determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages in lower tails by determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages below the respective demarcation voltage within the overlap regions;
• and
• adjusting threshold voltages of the identified memory cells in threshold voltage overlap regions to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells in threshold voltage overlap regions by lowering threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and increasing threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in lower tails such that the overlap regions reduce in size;
• the lowering threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails comprises:
• causing a positive drain-to-gate voltage at GIDL generation transistors in NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails by applying an erase voltage to bit lines connected to the NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and applying a GIDL generation voltage to the GIDL generation transistors in NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails, the GIDL generation voltage is lower than the erase voltage, and
• causing a negative drain-to-gate voltage at GIDL generation transistors in NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails by applying an erase inhibit voltage to bit lines connected to NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and applying a GIDL inhibit voltage to the GIDL generation transistors in NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails, the GIDL inhibit voltage is higher than the erase inhibit voltage, the erase inhibit voltage is lower than the erase voltage.

A non-volatile storage apparatus, comprising:

• a block of non-volatile memory cells of non-volatile memory cells configured to store a data set in overlapping threshold voltages distributions;
• and
• a control circuit connected to the block of non-volatile memory cells, the control circuit is configured to read the data set from the block of non-volatile memory cells and determine that the data set was not read successfully, in response to determining that the data set was not read successfully the control circuit is configured to:
• identify memory cells storing error bits by identifying memory cells in threshold voltage overlap regions between neighboring overlapping threshold voltages distributions;
• determine which of the identified memory cells in threshold voltage overlap regions have threshold voltages in upper tails by determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages above a respective demarcation voltage within the overlap regions;
• determine which of the identified memory cells in threshold voltage overlap regions have threshold voltages in lower tails by determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages below the respective demarcation voltage within the overlap regions;
• and
• adjust threshold voltages of the identified memory cells in threshold voltage overlap regions to be closer to centers of the overlapping threshold voltages distributions without changing threshold voltages distributions for the identified memory cells in threshold voltage overlap regions by lowering threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and increasing threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in lower tails such that the overlap regions reduce in size;
• the control circuit is configured to lower threshold voltages of memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails by:
• causing a positive drain-to-gate voltage at GIDL generation transistors in NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails by applying an erase voltage to bit lines connected to the NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and applying a GIDL generation voltage to the GIDL generation transistors in NAND strings that include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails, the GIDL generation voltage is lower than the erase voltage, and
• causing a negative drain-to-gate voltage at GIDL generation transistors in NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails by applying an erase inhibit voltage to bit lines connected to NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails and applying a GIDL inhibit voltage to the GIDL generation transistors in NAND strings that do not include the memory cells in threshold voltage overlap regions determined to have threshold voltages in upper tails, the GIDL inhibit voltage is higher than the erase inhibit voltage, the erase inhibit voltage is lower than the erase voltage.