Interleaved page buffers for inputting and outputting data with memory latches and status registers including a memory device
AssigneeSK hynix Inc.
InventorByoung Young Kim
Life of this patent
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Abstract
Provided herein is a memory device for inputting and outputting data and a memory system including the memory device and a memory controller. The memory device includes memory cells, a plurality of latches configured to sense a plurality of pieces of logical page data stored in the memory cells, and an operation controller configured to output a first latch select signal for selecting first latches, by which first logical page data among the plurality of pieces of logical page data is sensed, from among the plurality of latches in response to a first page data output command. The first latches output the first logical page data in response to the first latch select signal.
Claims17
A memory device, comprising:
- memory cells;
- a plurality of latches configured to sense a plurality of pieces of logical page data stored in the memory cells;
- and
- an operation controller configured to output a first latch select signal for selecting first latches, by which first logical page data among the plurality of pieces of logical page data is sensed, from among the plurality of latches in response to a first page data output command, and
- output a second latch select signal for selecting second latches, by which second logical page data among the plurality of pieces of logical page data is sensed, from among the plurality of latches in response to a second page data output command;
- and
- control the first latches to output the first logical page data to a data input/output circuit while the second latches sense the second logical page data from the memory cells,
- wherein the first latches output the first logical page data in response to the first latch select signal and the second latches output the second logical page data in response to the second latch select signal.
A memory system, comprising:
- a memory device including a plurality of latches configured to sense a plurality of pieces of logical page data stored in a physical page;
- and
- a memory controller configured to provide the memory device with a first page data output command that requests first logical page data among the plurality of pieces of logical page data,
- wherein the memory device is configured to:
- transmit the first logical page data from first latches to the memory controller in response to activation of a first latch select signal for selecting the first latches in which the first logical page data is stored among the plurality of latches;
- and
- sense second logical page data among the plurality of pieces of logical page data by second latches among the plurality of latches while transmitting the first logical page data from the first latches to the memory controller.
A memory device, comprising:
- memory cells;
- a plurality of latches coupled to the memory cells through bit lines;
- and
- a data input/output circuit configured to receive a plurality of pieces of logical page data from an external device;
- and
- an operation controller configured to:
- output a first latch select signal for selecting first latches, in which first logical page data among the plurality of pieces of logical page data to be stored in the memory cells is to be stored, from among the plurality of latches in response to a program command;
- and
- output a second latch select signal for selecting second latches, in which second logical page data among the plurality of pieces of logical page data to be stored in the memory cells is to be stored, from among the plurality of latches in response to the program command,
- wherein the first latches directly store the first logical page data from the data input/output circuit, and the second latches directly store the second logical page data from the data input/output circuit.
Dependencies are inferred from the claim text.