Three-dimensional memory and operating method thereof

A three-dimensional (3D) memory, comprising:

• a stacked structure, disposed on a dielectric substrate, and comprising a plurality of gate layers and a plurality of insulating layers alternately stacked, wherein each gate layer comprising a first gate and a second gate separated from each other;
• a plurality of annular channel layers, each corresponding to one of the plurality of gate layers and disposed between adjacent insulating layers;
• a p-type doped region, disposed in each annular channel layer and adjacent to the first gate;
• an n-type doped region, disposed in each annular channel layer and adjacent to the second gate;
• a source line pillar, disposed on the dielectric substrate, penetrating through the stacked structure, and located inside the annular channel layer to be in contact with the n-type doped region;
• a bit line pillar, disposed on the dielectric substrate, penetrating through the stacked structure, and located inside the annular channel layer to be in contact with the p-type doped region;
• a first gate insulating layer, disposed between the first gate and the annular channel layer;
• and
• a second gate insulating layer, disposed between the second gate and the annular channel layer.