Multi-program of memory cells without intervening erase operations
AssigneeMicron Technology, Inc.
InventorEzra Edward Hartz
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic causes first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first voltage distribution programmed relative to a first threshold voltage (Vt) level. The control logic causes, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level.
Claims17
A memory device comprising:
- an array of memory cells configured as single-level cell memory;
- and
- control logic operatively coupled with the array of memory cells, the control logic to perform operations comprising:
- causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising a first voltage distribution programmed relative to a first threshold voltage (Vt) level;
- causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level;
- and
- causing the plurality of memory cells to be erased after a predetermined number of programming operations have been performed at the plurality of memory cells without intervening erase operations.
A method comprising:
- causing, by control logic of a memory device comprising an array of memory cells configured as single-level cell memory, first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising a first voltage distribution programmed relative to a first threshold voltage (Vt) level;
- causing, by the control logic, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level;
- and
- causing, by the control logic, the plurality of memory cells to be erased after a predetermined number of programming operations have been performed at the plurality of memory cells without intervening erase operations.
A memory device comprising:
- an array of memory cells configured as multi-level cell memory;
- and
- control logic operatively coupled with the array of memory cells, the control logic to perform operations comprising:
- causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising multiple first voltage distributions programmed relative to multiple first threshold voltage (Vt) levels;
- causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising multiple second voltage distributions programmed relative to multiple second Vt levels, the multiple second Vt levels being higher than a highest Vt level of the multiple first Vt levels;
- and
- causing the plurality of memory cells to be erased after a predetermined number of programming operations have been performed at the plurality of memory cells without intervening erase operations.
Dependencies are inferred from the claim text.