Memory device using semiconductor element

A memory device using a semiconductor element, the memory device comprising:

• a first block in which a plurality of semiconductor memory cells including a first memory cell and a second memory cell are arranged in a matrix shape on a substrate,
• wherein the first memory cell includes a first semiconductor base extending parallel to the substrate,
• wherein the second memory cell includes a second semiconductor base separated from the first semiconductor base in a vertical direction or a horizontal direction and overlapping the first semiconductor base in plan view or in sectional view,
• wherein the first block includes
• a first impurity region and a second impurity region respectively continuous with one end and another end of the first semiconductor base,
• a third impurity region and a fourth impurity region respectively continuous with one end and another end of the second semiconductor base,
• a first gate insulating layer surrounding the first semiconductor base,
• a second gate insulating layer surrounding the second semiconductor base,
• a first gate conductor layer and a second gate conductor layer respectively in contact with a first side surface of the first gate insulating layer and a first side surface of the second gate insulating layer, the first gate conductor layer and the second gate conductor layer being continuous with each other and being arranged side by side, and
• a third gate conductor layer in contact with a second side surface of the first gate insulating layer and a second side surface of the second gate insulating layer, the second side surface of the first gate insulating layer and the second side surface of the second gate insulating layer respectively being opposite from the first side surface of the first gate insulating layer and the first side surface of the second gate insulating layer.