Memory structure and control method for reducing layout area of memory device

A control method of a memory device, comprising:

• arranging a plurality of first transistors arranged in a first array, wherein first ends of the first transistors are respectively coupled to a plurality of first bit lines, and gates of the first transistors are respectively coupled to a plurality of first word lines;
• arranging a plurality of second transistors arranged in a second array, wherein gates of the second transistors are respectively coupled to second ends of the first transistors, second ends of the second transistors are respectively coupled to a plurality of second bit lines, and first ends of the second transistors are respectively coupled to a plurality of second word lines;
• extending one of each of the first word lines and each of the first bit lines along a normal direction of a plane of the substrate to provide a first signal;
• and
• extending one of each of the second word lines and each of the second bit lines extended along a normal direction of a plane of the substrate to provide a second signal,
• wherein the first array comprises:
• N×M channel pillars, wherein N and M are positive integers;
• and
• M first conductive structures, wherein each of the first conductive structures surrounds N of the channel pillars, and each of the first conductive structures forms a common gate and each of the first word lines of the first transistors corresponding to the N channel pillars.

A memory structure, comprising:

• a plurality of first transistors arranged in a first array, wherein first ends of the first transistors are respectively coupled to a plurality of first bit lines, and gates of the first transistors are respectively coupled to a plurality of first word lines;
• and
• a plurality of second transistors arranged in a second array, wherein gates of the second transistors are respectively coupled to second ends of the first transistors, second ends of the second transistors are respectively coupled to a plurality of second bit lines, and first ends of the second transistors are respectively coupled to a plurality of second word lines,
• wherein the first transistors and the second transistors are disposed on a substrate, one of the each of the first word lines and each of the first bit line is extended along a normal direction of a plane of the substrate, and one of the each of the second word line and the each of the second bit lines is extended along the normal direction,
• wherein each of the first transistors is a gate all-around (GAA) transistor, and each of the second transistors is a channel all-around (CAA) transistor.