Apparatuses and methods for increased reliability row hammer counts
AssigneeMicron Technology, Inc.
InventorsHiroshi Akamatsu, Yuan He
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods increased reliability row hammer counts. Each word line of a memory may have an associated count value, stored in memory cells of the word line. Information in memory cells may be prone to change, such as from neutron strike. A counter circuit may decrease the count value each time the word line is accessed, since a decreasing count will tend to overestimate accesses due to error. A count error correction circuit may check the count value against redundant information and correct the count value if there is an error. Decreasing counts and count error correction may be used together to further increase reliability.
Claims19
An apparatus comprising:
- a word line intersecting a plurality of memory cells which are configured to store a count value;
- a first control circuit configured to receive the count value as part of an access operation on the word line and invert a logical state of the bits of the count value to generate an inverted count value;
- a count circuit configured to increase the inverted count value to generate an updated inverted count value;
- a second control circuit configured to receive the updated inverted count value and invert a logical state of the bits of the updated inverted count value to generate an updated count value, wherein the updated count value is written back to the plurality of memory cells.
A method comprising:
- reading a count value from memory cells along a word line, wherein the count value is associated with a number of accesses to the word line;
- inverting the count value;
- increasing the inverted count value;
- inverting the increased inverted count value to generate an updated count value;
- writing the updated count value back to the memory cells;
- and
- determining if the word line is an aggressor row based on the updated count value.
An apparatus comprising:
- a word line intersecting a plurality of memory cells which are configured to store a count value and redundant information, wherein the redundant information represents at least a portion of the bits of the count value;
- a count value correction circuit configured to receive the count value and the redundant information and to generate a corrected count value based on the count value and the redundant information;
- a counter circuit configured to update the corrected count value and determine if the word line is an aggressor based on the updated corrected count value, wherein the updated corrected count value is written back to the plurality of memory cells as the count value and the at least a portion of the bits of the corrected count value is written back to the plurality of memory cells as the redundant information.
Dependencies are inferred from the claim text.