Memory device including voltage generating circuit and operation method of memory device

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• a control logic circuit configured to generate a switching signal in response to a command received from an external device;
• and
• a voltage generating circuit including a first pump block, a second pump block, and a first common pump block,
• wherein, in response to the switching signal, the voltage generating circuit is configured to generate a first operating voltage by using the first pump block and the first common pump block and to generate a second operating voltage by using the second pump block and the first common pump block,
• wherein the first pump block includes a plurality of first unit pumps, and
• wherein the plurality of first unit pumps is connected to each other and has a first serial size and a first parallel size.

An operation method of a memory device, the method comprising:

• receiving an operation command from an external device;
• based on the operation command being a read command, performing a read operation based on a read voltage;
• and
• based on the operation command being a program command, performing a program operation based on a program voltage,
• wherein the memory device is configured to:
• connect a first pump block, a first common pump block, and a second common pump block in parallel with each other and generate the read voltage;
• and
• connect the first common pump block with a second pump block in series and generate the program voltage,
• wherein the first pump block includes a plurality of first unit pumps, and
• wherein the plurality of first unit pumps is connected to each other and has a first serial size and a first parallel size.